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Since the inherent serial nature of successive cancellation list (SCL) decoding results in a long latency, belief propagation (BP) decoding for polar codes has drawn attention for high-throughput applications. However, its error correction performance is inferior to that of SCL decoding. Therefore, the bit-flipping strategy has been recently applied to BP decoding, which can approach the SCL decoding performance through multiple additional decoding attempts. The original BP flip (BPF) decoding suffers from an inaccurate identification of erroneous bits by a fixed flip set (FS), which has been improved by the generalized BPF (GBPF) decoding. In this article, the GBPF decoding is extended to support multiple bits being flipped in one decoding attempt. In addition, for two types of decoding errors: detected errors and undetected errors, we propose two novel methods to more effectively identify erroneous bits. For detected errors, the concept of loop sets is defined and a loop-based identification method is introduced based on the study of error patterns of BP decoding. On the other hand, a method to generate a more accurate fixed FS is proposed for undetected errors, which considers the bit error distribution under BP decoding. Combining the two methods, the GBPF with merged sets (GBPF-MS) decoding can achieve the SCL-8 performance and outperforms the state-of-the-art BPF, BP list, and SC flip (SCF) decoding, for polar codes with length 1024 and information rate 1/2. Implemented by 40nm CMOS technology, the proposed GBPF-MS decoder with ten flips exhibits an average throughput of 4.19 Gbps at 2.5 dB, which is $1.6\times $ and $1.72\times $ faster than the state-of-the-art SCL-4 and SCF decoders, respectively. [ABSTRACT FROM AUTHOR]

Though belief propagation (BP) polar decoders can achieve higher throughput than successive-cancellation (SC)-based decoders, and how to efficiently generate different belief propagation decoders (BPDs) which can meet various design specifications remains challenging. To this end, an autogeneration, which can translate the generation formula of BPDs to efficient hardware implementations, has been proposed in this article. For different requirements, two BPD architectures have been given: 1) low-cost decoder (Type-I) and 2) high-throughput decoder (Type-II). The autogeneration of them can support different code rates, code lengths, and parallelisms. Synthesis results show that Type-I and Type-II provide higher throughput and hardware efficiency than the state-of-the-art (SOA) SC decoders. Moreover, compared to the SOA BPDs, both Type-I and Type-II achieve similar even better energy- and area-efficiency with a comparable throughput, for fully parallel configuration. With the autogeneration, we are able to obtain the design space regarding different design metrics, such as area efficiency, energy efficiency, and power density, within which the design optimization under given design constraints can be conducted. [ABSTRACT FROM AUTHOR]

Puncturing and shortening are two general ways to obtain an arbitrary code length and code rate for polar codes. When some of the coded bits are punctured or shortened, it is equivalent to a situation in which the underlying channels of polar codes are different. This fact calls for a general polar code construction, which is not yet available. In this article, a general construction of polar codes is studied in two aspects: 1) the theoretical foundation of the general construction and 2) the hardware implementation of general polar codes encoders. In contrast to the original identical and independent binary-input, memoryless, symmetric (BMS) channels, these underlying BMS channels can be different. The proposed general construction of polar codes is based on the existing Tal–Vardy’s procedure. The symmetric property and the degradation relationship are shown to be preserved under the general setting, rendering the possibility of a modification of Tal–Vardy’s procedure. Simulation results clearly show improved error performance with reordering using the proposed new procedures. Also, a novel encoding hardware architecture is proposed, which supports puncturing and shortening modes. Implementation results show the proposed encoder achieves approximately 30% throughput improvement when one quarter of bits are punctured/shortened. [ABSTRACT FROM AUTHOR]

The performance of belief propagation list (BPL) decoding of polar codes is related to the selection of $L$ factor graphs (FGs), which have the least number of girths. However, the straightforward search of such FGs is of high complexity. To achieve good performance with reasonable complexity, we propose an efficient method to find FGs with the least number of length-12 loops in all permuted FGs. Since some length-12 loops have been destroyed by redundant decoding operations, the corresponding FGs can be simplified to different numbers of length-12 loops. Thanks to the proposed loop simplification (LS), BPL decoding is now based on more efficient FGs, resulting in better performance and lower average decoding latency than the state-of-the-art. Numerical results have shown that the performance improvement is 0.15 dB when frame error ratio (FER) is $10^{-4}$ , for $(1024, 512)$ codes with $L=64$. [ABSTRACT FROM AUTHOR]

Due to its parallel propagation property, the belief propagation (BP) polar decoding can achieve high throughput and has drawn increasing attention. However, the BP decoding is not comparable with the successive cancellation list (SCL) decoding in terms of the error correction performance. In this brief, two BP flip (BPF) decoding algorithms are proposed. Compared with the existing BPF decoding, the generalized BPF (GBPF) decoding identifies error-prone bits more efficiently with a redefinition of bit-flipping. Furthermore, the GBPF decoding is optimized by decreasing the searching range by half, leading to the enhanced BP flip (EBPF) decoding with reduced complexity and improved performance for 5G polar codes. The hardware architecture is provided and implemented using SMIC 65nm CMOS technology. The results show that, compared with the state-of-the-art SC flip decoders, the proposed EBPF decoder exhibits 30% throughput improvement under comparable error correction performance. [ABSTRACT FROM AUTHOR]

As the first provably capacity-achieving codes, polar codes have been selected as the coding scheme for 5G enhanced mobile broadband (eMBB) control channels. Furthermore, if the bottleneck in decoding complexity is addressed, polar codes are still promising for long code length scenarios in the future with superior error-correcting performance. Considering the demand of cloud radio access network (C-RAN) in 5G system, the low-latency software polar decoder is studied in this paper. Two novel algorithms are proposed to reduce the latency of the successive cancellation list (SCL) decoding, including the segmented list-pruning (SLP) algorithm and the modified distributed sorting (MDS) algorithm. Moreover, the proposed SLP algorithm improves the decoding performance compared to existing segmentation schemes. In terms of the software implementation, our decoder is nearly $20\%$ faster than the state-of-the-art flexible software polar list decoder. [ABSTRACT FROM AUTHOR]