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The feasibility of creating top- and bottom-gate pentacene organic field-effect transistors (OTFTs) of comparable performance through the vapor-phase deposition of parylene onto existing pentacene OTFTs on Si/SiO2 is demonstrated. The dependence of the electrical properties on carrier concentration and temperature suggests that, despite differences in interface chemistry and roughness, similar mechanisms are responsible for limiting transport both within the channel and at the metal-organic contacts in both top- and bottom-gate devices.

Gated four-probe measurements designed to measure contact resistance in petacene-based organic thin-film transistors (OTFTs) are described. TFTs through gated four-probe measurements are studied as a function of contact metallurgy substrate chemistry, gate bias, and temperature.

Structural and electrical properties in thin films of an n-channel organic semiconductor, N,N'-dipentyl 3,4,9,10-perylene tetracarboxylic dimide (PTCDI-C5) are discussed. A model is proposed to explain positive TVS in gate bias stress and oxygen exposure experiments which is based on the formation of a metastable complex between PTCDI-C5 and oxygen, that creates a deep acceptor-like strap state

In this letter we report the use of roughly polished aluminum substrates with spin-coated polymer-smoothing layers for the fabrication of pentacene field-effect transistors. Transistors with spin-coated poly(methylmethacrylate) gate insulator layers were fabricated and showed good performance. On the gate insulator surface, the root-mean-square roughness was found to be 0.18 nm, significantly smaller than the aluminum surface roughness, which is on the scale of tens of nanometers. Field-effect carrier mobilities extracted from the device data reached 0.75 cm2 V-1 s-1; the maximum on/off current ratio was near 5×106. [ABSTRACT FROM AUTHOR]