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The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected. [ABSTRACT FROM PUBLISHER]

A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 \muV/e^- to 50 \muV/e^- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e^- for a peaking time Tp=115\ ns and Cdet=1.2\ pF. With a DC-coupled CdTe detector, the ENC is 210 e^-\ rms for a peaking time Tp=380\ ns and Cdet=2\ pF and the leakage current Idleak=0.15\ nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e^-\ rms (at one sigma level). The ASIC is designed in a CMOS 0.35 \mum technology and its total area is 4800\times 5000\ \mum^2. [ABSTRACT FROM AUTHOR]