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Spectrally selective X-ray imaging provides improved material and tissue discrimination in comparison with the state-of-the-art dual energy technologies that are commonly used in medical, industrial, and security applications. Cadmium telluride (CdTe)- and cadmium zinc telluride (CdZnTe)-based line scanners and small size two-dimensional X-ray sensors are emerging to the market, but the need for large-scale panels is axiomatic. In this study, a seamless CdTe tile was developed that enables the implementation of large-sized, energy selective X-ray detector panels. The developed tile consists of a $64\times64$ pixel array (with $150~\mu \text{m}$ pitch) with a necessary substrate, ASIC, and CdTe crystal. The performance of the constructed seamless tile was characterized by focusing on spectral resolution and stability. In addition, a simple pixel trimming method that automates the equalization of each energy selective pixel was developed and analyzed. The obtained results suggest that the proposed concept of seamless (tileable) detector structures is a feasible approach to scale up panel sizes. The seamless tile shows comparable spectral resolution and stability performance with commercial CdTe sensors. The effect of tile to tile variation, the realization of a large-scale panel, as well as the charge sharing performance were left out of the scope and are to be studied in the next phase. [ABSTRACT FROM AUTHOR]

This paper presents the design of a PXF40—an ultrafast single photon-counting (SPC) readout front-end electronics implemented in a CMOS 40-nm technology dedicated to hybrid pixel detectors. The prototype application specific integrated circuit core is a matrix of 432 pixels ($24\times 18$) with a $100\,\,\mu \text {m}\times 100\,\,\mu \text{m}$ size. The single processing channel consists of a charge-sensitive amplifier (CSA), a discriminator, and a 24-bit counter with logic circuitry. The input signal is amplified and formed only by the CSA stage. Depending on the CSA input transistor current value, it can operate in two modes: FAST and FAST_HC with higher current. The measured power dissipation per channel $P = 45 \,\,\mu \text{W}$ and noise $\text {ENC} = 212\,\, \text {e}^{-}$ rms for the FAST mode, while $P=100\,\,\mu \text{W}$ and ENC = 185 e− rms for the FAST_HC mode, respectively. The readout chip can count up to 1.2 Gcps/mm2 based on 10% dead-time loss input rate parameter, which is currently the fastest SPC-based solution. [ABSTRACT FROM AUTHOR]

The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500- \mu \textm -thick silicon sensor, a two-tier 34- \mu \textm -thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1- \mu \textm -diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80- \mu \textm -pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn-Pb balls placed on a 320- \mu \textm pitch, yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 \mu \textW . A successful completion of the 3-D integration is reported. In addition, all pixels in the matrix of 64\times 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 \text{e}^{-} rms and a conversion gain of 69.5 \mu \text{V}/\text{e}^{-} with 2.6 \texte^- rms and 2.7 \mu \textV/\texte^- rms pixel-to-pixel variations, respectively, were measured. [ABSTRACT FROM AUTHOR]

The Vertically Integrated Photon Imaging Chip (VIPIC) project explores opportunities of the three-dimensional integration for imaging of X-rays. The design details of the VIPIC1 chip are presented and are followed by results of testing of the chip. The VIPIC1 chip was designed in a 130 nm process, in which through silicon vias are embedded right after the front-end-of-line processing. The integration of tiers is achieved by the Cu-Cu thermo-compression or Cu-based oxide-oxide bonding. The VIPIC1 readout integrated circuit was designed for high timing resolution, pixel based, X-ray Photon Correlation Spectroscopy experiments typically using 8 keV X-rays at a synchrotron radiation facility. The design was done for bonding a Silicon pixel detector, however other materials can be serviced as long as the positive polarity of charge currents is respected. [ABSTRACT FROM PUBLISHER]