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Performance and reliability comparison of oxide-based thin-film transistors fabricated at a maximum process temperature of 115 °C is presented. A fully patterned and passivated process was successfully evaluated and implemented using polycrystalline ZnO and amorphous indium–gallium–zinc–oxide (IGZO) as an active layer in glass substrates. Saturation mobilities of 14.2 and 9.0 cm $^{{2}}\cdot \text{V}^{-{1}}\cdot \text{s}^{-{1}}$ were obtained for ZnO and IGZO, respectively, with threshold voltages of 2.2 and 2.0 V, an ON/ OFF ratio $> {1} \times 10^{{8}}$ , and an ${I}_{{\text {off}}}< {1} \times 10^{-{12}}$ A. The small mobility change in IGZO with gate voltage is due to its amorphous character. Longer variation is observed in polycrystalline ZnO due to its grain boundaries. Reliability studies show a threshold voltage shifting of 0.4 and 1.8 V for ZnO and IGZO devices, testing after 1200-s stress. Devices were successfully implemented in ZnO- and IGZO-based inverters using saturation and zero-drive structures, showing a maximum dc gain of 2.4- and 25-V/V, respectively. [ABSTRACT FROM AUTHOR]

In this work, the performance of inkjet-printed 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic thin-film transistors (OTFTs) was studied under various printing conditions using photolithography-defined test structures. OTFTs were printed from TIPS-pentacene solutions with several concentrations, and the impact of printing temperature as well as the amount of material printed was studied. A hybrid approach that includes wells defined by a photolithography process and printed TIPS solution is demonstrated. The results show that the mobility of the printed OTFTs increases with increasing solution concentration, with a maximum mobility for concentration of 50 mg/mL and substrate temperature of 50°C. X-ray diffraction analysis showed the presence of the thin-film phase for all of the TIPS concentrations, with strong and sharp preferential orientation along the (001) direction without any disruption in molecular packing with increasing TIPS thickness. Optimized OTFTs fabricated with this technique show mobilities of 5 × 10 cm/V-s, threshold voltages ( V) in the range of −5 V, and subthreshold slopes of approximately 0.5 V/dec. On-off current ratios up to 10 were also achieved. [ABSTRACT FROM AUTHOR]

In this paper, we report a feasibility study of MuGFETs (multi-gate field effect transistors) devices using solution-based cadmium sulfide films as the semiconductor. The simulations were carried out using the commercially available ATLAS simulator. Experimental parameters for CdS were extracted from planar thin film transistors fabricated using photolithography methods. Several critical design parameters for MuGFETs devices were studied, including fin width, fin high, channel length, and CdS carrier concentration. Short-channel effects can be reasonably controlled by reducing either fin height or width. It is shown that is possible to fabricate devices that operate in depletion or enhancement mode by controlling the device structure. ION/IOFF ratio was in the range 108–1010, subthreshold slope was closely related to the geometry of the MuGFET. We also observed that as the CdS carrier concentration decreases, the on-voltage shifts to positive values. Optimized MuGFETs simulated in enhancement mode show excellent subthreshold slope, and ION/IOFF ratio ∼1010. This study demonstrates that CdS can be used to fabricate enhanced mode/depletion mode devices using solution-based semiconductors. Furthermore, all processing is kept at temperatures below 100 °C, which demonstrates that these devices can be used in flexible substrates. [ABSTRACT FROM AUTHOR]

Abstract: The fabrication and characterization of transparent logic inverters based on zinc oxide (ZnO) thin film transistors (TFTs) is reported. The inverters are fabricated using standard photolithographic techniques on glass substrates, and the entire fabrication process temperature is maintained <100°C, which render the devices suitable for flexible and transparent electronics applications. Pulsed laser deposition is used to deposit aluminum-doped zinc oxide and ZnO as electrode and active semiconductor materials, respectively. Electrical characterization for individual TFTs demonstrate mobilities of ~10cm2/V-s, threshold voltages of 6V, sub-threshold slopes of 630mV/decade and I ON/I OFF ratios of 5×106. Films characterized by UV-Vis showed optical transmission >80% in the visible spectrum. The inverters are analyzed with AC input signals at frequencies of 100 and 500Hz. The AC response shows an average rise and fall time transitions of 0.65 and 0.44ms, respectively. Measured inverters delay is in the order of 0.21ms. [Copyright &y& Elsevier]

Abstract: In this work we present a new polymeric thin film transistor (PTFT), fabrication process where standard photolithographic and dry etching techniques are used to place gate contact on the upper surface of the device, and to access in an easy and reliable way the buried bottom drain and source contacts from the upper surface of the device. This fabrication technique benefits of all the advantages that photolithographic processes report, as device isolation, patterning of small dimensions and possibility of device integration on both rigid and flexible substrates. We also show that, since PMMA is placed as the outermost polymeric layer, it serves both as dielectric and as protective layer, allowing devices to work in ambient conditions with significantly less degradation than other PTFTs structures previously reported. Electrical characterization of the devices showed that this technological approach provides mobility values an order of magnitude higher than those previously reported by us, using the same polymeric layers, but with buried drain and source contacts. [Copyright &y& Elsevier]

Thin film transistors (TFTs) with a bottom-gate configuration were fabricated using a photolithography process with chemically bath deposited (CBD) cadmium sulfide (CdS) films as the active channel. Thermal annealing in hydrogen was used to improve electrical stability and performance of the resulting CdS TFTs. Hydrogen thermal treatments results in significant VT instability (VT shift) improvement while increasing the Ion/Ioff ratio without degrading carrier mobility. It is demonstrated that after annealing VT shift and Ion/Ioff improves from 10 V to 4.6 V and from 105 to 109, respectively. Carrier mobility remains in the order of 14.5 cm2 V s−1. The reduced VT shift and performance is attributed to a reduction in oxygen species in the CdS after hydrogen annealing, as evaluated by Fourier transform infrared spectroscopy (FTIR). [ABSTRACT FROM AUTHOR]