Search

This study focused on the design principle and implementation of a high-frequency, wide-range frequency synthesizer by using a dual control path phase-lock loop (PLL) and a varactorless oscillator controlled by inductive–capacitive (LC-type) voltage (i.e., a voltage-controlled oscillator, VCO). Without a varactor in the LC tank, the tuned-transducer oscillator with Q-enhanced functionality can easily arrive at the requirements of high-frequency wide-range low-noise operations. We utilized a difference tuned varactorless VCO to create two different KVCOs and applied it to a dual control path PLL architecture to obtain wide tuning range and more favorable phase noise. In addition, a high-speed current-mode logic divider was employed given its high speed (because of the use of a transformer inductor), extremely high operation frequency, and wide-range. The proposed PLL was assembled using the standard 0.13-μm CMOS technology on a 0.95 × 1.05 mm2 chip. The PLL dissipated 40 mW at a 1.2 V supply. The measurement of phase noise at 17.64 GHz was − 98.12 dBc/Hz at a 1 MHz offset.

This paper discusses the design and fabrication of a high-frequency wide-range frequency synthesizer based on a phase locked loop (PLL), varactorless LC-type voltage-controlled oscillator, and push-push frequency doubler. In addition, a high-speed programmable divider using multiphase selection is employed for channel switching. The proposed circuits were fabricated in a standard 90-nm CMOS process with a chip area of 0.8mm?1.1mm. The PLL dissipated 60mW when the supply was 1.2V. The measured phase noise of the frequency synthesizer at a frequency of 17.64GHz and offset of 1MHz was -97dBc/Hz. The work comprises a varactorless VCO, frequency doubler, and programmable divider.Channel switching uses a multiphase selection, high-speed programmable divider.The VCO uses a tunable transformer-base inductor and novel varactorless technique.

To lower the supply voltage for high-frequency operation, a fully integrated frequency synthesizer, together with regenerative frequency-doubling and fractional phase-rotating techniques, is presented. The frequency-doubling circuit regenerates the tail signals at twice the frequency of the quadrature voltage-controlled oscillator (QVCO) to achieve larger output swing and higher operating frequency for the synthesizer. Additionally, a hybrid circuit utilizing a new folded regime for the first-stage divider and the phase-rotating circuit is developed in the prescaler. Under full-speed operation, the QVCO with the frequency doubler and the divider can work from a 0.5-V supply, whereas the synthesizer dissipates 12 mW. At 9.1-GHz carrier frequency, the measured phase noise is -104.5 dBc/Hz from 1-MHz offset.

Implemented in a standard 0.18-μm CMOS process, a 0.8/0.9-V 5.4-GHz low-power phase-locked loop (PLL) is presented. In the prescaler, the first-stage divide-by-2 prescaler is structed with LC-type VCO by inductance coupled to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. As the building blocks are optimized for low-voltage and low-power operations, the fabricated 5.4-GHz PLL consumes a dc power of 4.8 mW from a 0.8/0.9-V and phase noise of −109.6 dBc/Hz at 1-MHz offset.

Without an extra on-chip accumulation-mode MOS varactor, a voltage-controlled oscillator (VCO) using a negative-transconductance back-gate tuned technique is demonstrated in a standard 0.18 μm CMOS process to achieve low-voltage, wide-range and high-frequency designs. Employing the varied p-n junction capacitance and the varied transconductance in the intrinsic-tuned regime, the VCO provides the tuning range of 9.95 to 11.05 GHz at a 0.6 V supply and dissipates below 4.35 mW. At 11 GHz carrier frequency, the measured phase noise is -110.4 dBc/Hz at a 1 MHz offset.

The paper addresses the design and realization of a high-frequency and wide range frequency synthesizer based on a PLL together with a varactorless LC-type VCO and a push-push frequency doubler. In addition, a high-speed programmable divider using multi-phase selection is employed for channel switching. The proposed circuits were fabricated in a standard 90-nm CMOS process with a chip area of 0.8×1.1 mm2. The PLL dissipates 60 mW at a 1.2-V supply. The measured phase noise of the doubler at 35.28-GHz frequency is -90.42 dBc/Hz at a 1-MHz offset.

Fabricated in a 0.18-µm CMOS technology, a wide-range fractional-N frequency synthesizer with a phase-compensated technique is presented. While using a 630–960 MHz LC-type VCO, the synthesizer can provide the range of 55 to 960 MHz with a band-selecting structure to satisfy the ATSC applications. Using the phase-rotating concept, the synthesizer can achieve the fractional functionality, instead of the conventional ΔΣ interpolation. The measured results show phase noise is −123 dBc/Hz at 1-MHz offset. The lock time is below 6 µs from 640 MHz to 930 MHz.