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Segmented-channel \Si1 - x\Gex/\Si p-channel MOSFETs are fabricated using a conventional process, starting with corrugated \Si1 - x\Gex/\Si substrates. As compared with the control devices fabricated using the same process but starting with a noncorrugated \Si1 - x\Gex/\Si substrate, the segmented-channel MOSFETs show better layout efficiency (30% higher ION for IOFF = \10\ \nA per micrometer layout width) due to enhanced hole mobility and dramatically reduced dependence of performance on layout width due to the geometrical regularity of the channel region. [ABSTRACT FROM AUTHOR]

Reverse back biasing of a planar germanium-on-insulator tunneling field-effect transistor provides for significant improvement in ION/IOFF, by over an order of magnitude for 0.25 V operating voltage. Optimization of the gate-to-source overlap and source doping gradient is key to maximizing the benefit of back biasing. [ABSTRACT FROM PUBLISHER]

The stress transfer efficiency (STE) and impact of process-induced stress on carrier mobility enhancement in aggressively scaled FinFETs are studied for different stressor technologies, substrate types, and gate-stack formation processes. TCAD simulations show that strained-source/drain STE is \1.5\times larger for bulk FinFETs than for SOI FinFETs. Although a gate-last process substantially enhances longitudinal stress within the channel region, it provides very little improvement in electron mobility over that achieved with a gate-first process. Guidelines for FinFET stressor technology optimization are provided, and performance enhancement trends for future technology nodes are projected. [ABSTRACT FROM PUBLISHER]

The inversion-layer hole mobility in MOSFETs with thin silicon–germanium (\Si1 - x\Gex) channels grown pseudomorphically on Si is calculated using a self-consistent \6 \times \6\ k \cdot p Poisson–Schrödinger mobility simulator calibrated to experimental and simulation data. The addition of uniaxial compressive stress to the inherent biaxial compressive strain of the pseudomorphic \Si1 - x\Gex layer is found to further enhance hole mobility by up to 2.5\times. Two-dimensional device simulations are used to assess the benefit of the \Si1 - x \Gex heterostructure channel for boosting the on -state current (Ion) of p-channel MOSFETs with a gate length (Lg) of 18 nm; the results show a moderate (10%–40%) improvement over a bulk-Si MOSFET. [ABSTRACT FROM PUBLISHER]

Drift-diffusion models are used in conjunction with Monte Carlo simulations to study and compare the scalability of germanium (Ge) versus silicon (Si) p-channel double-gate MOSFETs near the end of the technology roadmap. Direct source-to-drain tunneling (DSDT) and uniaxial compressive stress effects are taken into account. The higher dielectric constant of Ge results in degraded short-channel effects and lower drive currents for a given off-state leakage specification. With large compressive uniaxial channel stress (1.5 GPa), Ge can outperform Si for gate lengths (Lg) greater than 15 nm. Due to its lower effective hole transport mass, Ge suffers more from DSDT, resulting in degraded p-channel MOSFET performance at very short Lg. [ABSTRACT FROM PUBLISHER]