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Your search keyword '"Heirman, Wim"' showing total 2 results
Start Over Author "Heirman, Wim" Topic performance analysis
2 results on '"Heirman, Wim"'

1. Multi-Stage CPI Stacks.

Author

Eyerman, Stijn, Heirman, Wim, Du Bois, Kristof, and Hur, Ibrahim

Abstract

CPI stacks are an intuitive way to visualize processor core performance bottlenecks. However, they often do not provide a full view on all bottlenecks, because stall events can occur concurrently. Typically one of the events is selected, which means information about the non-chosen stall events is lost. Furthermore, we show that there is no single correct CPI stack: stall penalties can be hidden, can overlap or can cause second-order effects, making total CPI more complex than just a sum of components. Instead of showing a single CPI stack, we propose to measure multiple CPI stacks during program execution: a CPI stack at each stage of the processor pipeline. This representation reveals all performance bottlenecks and provides a more complete view on the performance of an application. Multi-stage CPI stacks are easy to collect, which means that they can be included in a simulator with negligible slowdown, and that they can be included in the core hardware with limited overhead. [ABSTRACT FROM PUBLISHER]

Published
2018
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2. Using fast and accurate simulation to explore hardware/software trade-offs in the multi-core era

Author

Heirman, Wim, Carlson, Trevor, Sarkar, Souradip, Ghysels, Pieter, Vanroose, Wim, and Eeckhout, Lieven

Subjects
Technology and Engineering, Architectural simulation, performance analysis, software optimization, Mathematics
Abstract

Writing well-performing parallel programs is challenging in the multi-core processor era. In addition to achieving good per-thread performance, which in itself is a balancing act between instruction-level parallelism, pipeline effects and good memory performance, multi-threaded programs complicate matters even further. These programs require synchronization, and are affected by the interactions between threads through sharing of both processor resources and the cache hierarchy. At the Intel Exascience Lab, we are developing an architectural simulator called Sniper for simulating future exascale-era multi-core processors. Its goal is twofold: Sniper should assist hardware designers to make design decisions, while simultaneously providing software designers with a tool to gain insight into the behavior of their algorithms and allow for optimization. By taking architectural features into account, our simulator can provide more insight into parallel programs than what can be obtained from existing performance analysis tools. This unique combination of hardware simulator and software performance analysis tool makes Sniper a useful tool for a simultaneous exploration of the hardware and software design space for future high-performance multi-core systems.

Published
2011

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