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A study of carrier transport in top-gate and bottom-contact TIPS-pentacene organic field-effect transistors (OFETs) based on mobility is presented. Among three mobilities extracted by different methods, the low-field mobility obtained by the Y function exhibits the best reliability and ease for use, whereas the widely applied field-effect mobility is not reliable, particularly in short-channel transistors and at low temperatures. A detailed study of contact transport reveals its strong impact on short-channel transistors, suggesting that a more intrinsic transport analysis is better implemented in relatively longer-channel devices. The observed temperature dependences of mobility are well explained by a transport model with Gaussian-like diffusivity band tails, different from diffusion in localized states band tails. This model explicitly interprets the non-zero constant mobility at low temperatures and clearly demonstrates the effects of disorder and hopping transport on temperature and carrier density dependences of mobility in organic transistors. [ABSTRACT FROM AUTHOR]

A modeling of organic field-effect transistors' (OFETs') electrical characteristics is presented. This model is based on a one-dimensional (1-D) Poisson's equation solution that solves the potential profile in the organic semiconducting film. Most importantly, it demonstrates that, due to the common open-surface configuration used in organic transistors, the conduction occurs in the film volume below threshold. This is because the potential at the free surface is not fixed to zero but rather rises also with the gate bias. The tail of carrier concentration at the free surface is therefore significantly modulated by the gate bias, which partially explains the gate-voltage dependent contact resistance. At the same time in the so-called subthreshold region, we observe a clear charge trapping from the difference between C-V and I-V measurements; hence a traps study by numerical simulation is also performed. By combining the analytical modeling and the traps analysis, the questions on the C-V and I-V characteristics are answered. Finally, the combined results obtained with traps fit well the experimental data in both pentacene and bis(triisopropylsilylethynyl)-pentacene OFETs. [ABSTRACT FROM AUTHOR]

Abstract: Recent fundamental research on nano-scale interface control for organic thin film transistors is presented. The interfaces between the organic channel and the substrate, and between the organic channel and the metal electrodes have the greatest influence on transistor performance. The interface properties also drastically change the operation-stability of the transistor performance. This paper shows the results of a series of experimental investigations on the interfaces in the pentacene OTFT. [Copyright &y& Elsevier]

The growth control of pentacene thin films on SiO2/Si substrates is investigated by focusing on the relationship between the grain structure and flatness of the film surface. Pentacene thin films showing various grain structures are reproducibly controlled by changing the evaporation flux rate and substrate temperature. Atomic force microscopy analysis of the film surface indicates that the surface roughness is strongly related to the growth condition. In addition, flat-topped grains grown layer by layer are obtained among controlled grain structures, and a maximum grain size of 25 μm2 is obtained. The surface roughness significantly decreases for the flat-topped grain. [Copyright &y& Elsevier]

Close correlation between low-frequency noise and charge transport in pentacene transistors is observed. The trap density evolving with pentacene deposition reveals transformation of growth phase and different transport mechanisms. It explains the greatly altered mobility and contact resistance in which the upper surface's trapping plays an important role. Inspecting contact noise shows high density of traps at contacts that result possibly from pyramid like growth of pentacene or contact damage or both. [ABSTRACT FROM AUTHOR]

We fabricate high-performance pentacene thin-film transistors (TFTs) using lithographic processes compatible with industry standard amorphous silicon (a-Si) TFT fabrication. Bottom-contact bottom-gate pentacene TFTs realized with silicon nitride (\SiNx) gate dielectric show effective mobility values of 0.59 \cm^2/\Vs, contact resistances as low as 2.4 \k\Omega \cdot \cm , and low threshold voltages. These results demonstrate the viability of using \SiNx as a gate dielectric for vacuum-deposited organic TFTs for large-area and flexible electronic applications. [ABSTRACT FROM PUBLISHER]

Frequency response measurements were performed on top-contact pentacene organic thin-film transistors (OTFTs). The ac characteristics of OTFTs are strongly limited by the contact interface between a metallic electrode and a pentacene thin film. Local doping of a charge transfer molecule (CTM) into the contact interface efficiently improves the ac characteristics. Metal-insulator-semiconductor capacitance measurements revealed that the interface contains parasitic impedance composed of capacitance and resistance in parallel. The parasitic impedance was suppressed by CTM doping of the interface. The limitation factors for the frequency of operation in such an OTFT are discussed based on the experimental results and an equivalent circuit model. [ABSTRACT FROM AUTHOR]

We present pentacene thin-film transistors with poly-para-xylylene gate dielectric and passivation films for plastic electronics. Both the poly-para-xylylene films are formed by dry chemical vapor deposition at room temperature. An organic pentacene channel is fully encapsulated by poly-para-xylylene films, except in the area of electrode connection. Passivation induces little degradation of the organic transistor properties. In addition, a small amount of charge transfer molecules are introduced between the pentacene channel and the metal electrodes to improve device performance. Contact resistance is sufficiently reduced by the employment of the charge transfer molecules, which is analyzed using a transmission-line model. [ABSTRACT FROM AUTHOR]

A surface treatment method has been developed for the SiO2/Si substrate to control the electrical properties of pentacene thin-film transistors (TFTs). The surface treatment is performed by spin-coating 1,1,1,3,3,3-hexamethyldisilazane liquid, resulting in a drastic improvement of the off current although the surface treatment never shows a pronounced morphological change in the pentacene channel in comparison with the one on the nontreated substrate. The off current improvement directly enhances the transistor performance especially in the TFTs with a few monolayers channel thickness. The off current suppression could be caused by the reduction of the interfacial floating charge trapped at the pentacene/SiO2 interface. [ABSTRACT FROM AUTHOR]

A surface treatment method has been developed for the SiO2/Si substrate to control the electrical properties of pentacene thin-film transistors (TFTs). The surface treatment is performed by spin-coating 1,1,1,3,3,3-hexamethyldisilazane liquid, resulting in a drastic improvement of the off current although the surface treatment never shows a pronounced morphological change in the pentacene channel in comparison with the one on the nontreated substrate. The off current improvement directly enhances the transistor performance especially in the TFTs with a few monolayers channel thickness. The off current suppression could be caused by the reduction of the interfacial floating charge trapped at the pentacene/SiO2 interface. [ABSTRACT FROM AUTHOR]

A pentacene nanocrystal transistor with carbon nanotube electrodes as a nanosize source and drain was realized. In the device fabrication, the evaporated pentacene selectively grew around the nanotube electrodes. This may be caused by the common nanounit combination of the carbon six-membered ring contained in the pentacene and the nanotube. The nanotransistor showed controllable transistor operation at room temperature and Coulomb blockade oscillations at 4.2 K in gate voltage characteristics. [ABSTRACT FROM AUTHOR]

We established a dry-etching patterning process for the channel formation of pentacene thin-film transistor, and fabricated a four-terminal device equipped with a gate electrode. The four-terminal device enabled us to divide two-terminal source–drain resistance into two components of contact resistance and pentacene channel resistance. We obtained direct evidence of a gate-voltagedependent contact resistance change: the gate-induced charge significantly reduced the contact resistance and increased source–drain current. Furthermore, the temperature dependence of the device clearly indicated that the contact resistance was much higher than the channel resistance and was dominated in the two-terminal total resistance of the device below 120 K. An observed activation energy of 80 meV for contact resistance was higher than that of 42 meV for pentacene channel resistance. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Abstract: Measurements of power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors reveal the preponderance of a 1/f-type PSD behavior with the amplitude varying as the squared transistor gain and increasing as the inverse of the gate surface area. Such features impose an interpretation of LFN by carrier number fluctuations model involving capture/release of charges on traps uniformly distributed over the gate surface. The surface slow trap density extracted by the noise analysis is close to the surface states density deduced independently from static I(V) data, which confirms the validity of the proposed LFN interpretation. Further, we found that the trap densities in bottom-contact (BC) devices were higher than in their top-contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in the contact regions in particular. At the highest bias the noise originating from the contact resistance is also shown to be a dominant component in the PSD, and it is well explained by the noise originating from a gate-voltage dependent contact resistance. A gate area scaling was also performed, and the good scaling and the dispersion at the highest bias confirm the validity of the applied carrier number fluctuations model and the predominant contact noise at high current intensities. [Copyright &y& Elsevier]

Abstract: A study of the contact resistance (R sd) in pentacene-based double-gate transistors is presented. In top-contact transistors, as the negative bias of the additional top-gate bias is increased, R sd decreases by over five orders of magnitude for small bottom-gate voltages. In bottom-contact transistors, R sd is reduced by about ten times for all bias values, implying improved charge transport in all operating regimes. The different tunability of R sd in top/bottom-contact transistors is attributed to different charge injection modulation by the coplanar/staggered top gate. Therefore, double-gate architecture offers a novel and effective approach to limit R sd and its relevant impacts on organic transistor. [Copyright &y& Elsevier]