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1. Study of the Radio Frequency (RF) performance of a Wafer-Level Package (WLP) with Through Silicon Vias (TSVs) for the integration of RF-MEMS and micromachined waveguides in the context of 5G and Internet of Things (IoT) applications. Part 2: parameterised 3D model and optimisation

2. Study of the Radio Frequency (RF) performance of a Wafer-Level Package (WLP) with Through Silicon Vias (TSVs) for the integration of RF-MEMS and micromachined waveguides in the context of 5G and Internet of Things (IoT) applications: Part 1—validation of the 3D modelling approach

3. A modelling and simulation approach for radio frequency (RF) parasitic effects reduction in wafer-level packaging (WLP) of RF-MEMS passive components.

4. Fast simulation of an RF-MEMS toggle-switch through a behavioural models software library of elementary components.

5. RF-MEMS for 5G applications: a reconfigurable 8-bit power attenuator working up to 110 GHz. Part 2—Experimental characterisation of the RF behaviour.

6. RF-MEMS for 5G applications: a reconfigurable 8-bit power attenuator working up to 110 GHz. Part 1: design concept, technology and working principles.

7. Reconfigurable RF-MEMS-based impedance matching networks for a hybrid RF-MEMS/CMOS class-E power amplifier.

8. RF-MEMS Technology for 5G: Series and Shunt Attenuator Modules Demonstrated up to 110 GHz.

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