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We propose to use knowledge about a parallel application's structure that was acquired with the use of a skeleton based development strategy to dynamically improve its performance. Parallel/distributed programming provides the possibility of solving highly demanding computational problems. However, this type of application requires support tools in all phases of the development cycle because the implementation is extremely difficult, especially for non-expert programmers. This work shows a new strategy for dynamically improving the performance of pipeline applications. We call this approach Dynamic Pipeline Mapping (DPM), and the key idea is to have free computational resources by gathering the pipeline's fastest stages and then using these resources to replicate the slowest stages. We present two versions of this strategy, both with complexity O(Nlog(N)) on the number of pipe stages, and we compare them to an optimal mapping algorithm and to the Binary Search Closest (BSC) algorithm [1]. Our results show that the DPM leads to significant performance improvements, increasing the application throughput up to 40% on average.

There are several parallel applications that are implemented using a Master/Worker parallel/distributed programming paradigm. Applications using this predefined programming structure can be easily implemented using message passing programming libraries (MPI). Moreover, the multicore features present nowadays on CPU architecture can be exploited at the node level by applying thread parallelism (OpenMP). In order to exploit the benefits of both two levels of parallelism, the Master/Worker applications can be implemented as hybrid applications. However, reaching the expected performance indexes is not trivial because there are several parameters (number of nodes, number of threads per node, thread affinity and data distribution among all nodes) that must be tuned for each particular application or even during its execution to reach a successful performance. On the other hand, the application workload may change drastically during successive executions, so those parameters need to be modified according to this behavior. Additionally, cache memory architecture in multicore systems directly influences the performance and this behaviour must be deeply analysed. In this paper we present a proposal to model the performance of hybrid Master/Worker applications on multicore systems considering the issues outlined above. In particular, this model determines dynamically at runtime the configuration of the appropriate number of workers and threads of the hybrid application to achieve the best possible performance.

Parallel computing teaching has an important difficulty, there are few tools to directly learn the behavior of the parallel algorithms and the parallel architectures. Normally the student is formed to think in sequential algorithms running in sequential machines. We present PSEE, a tool to reduce the gap between the basic concepts and its utilization. PSEE is an integrated and interactive graphic environment which allows to simulate and evaluate the performance of parallel algorithms in parallel architectures. PSEE permits to manage the main characteristic parameters involved in the system in order to show the tuning grade of the algorithm/architecture couple. PSEE includes a graphic editor for algorithms and architectures in modelled form, an interactive simulator to run (simulate) the algorithm on the architecture and a performance evaluation instrument.

Our objective is to show a parallel system development method within the educational area based on the Parallel System Development Environment (PSEE). To do so, first we define the development cycle proposed by PSEE, and the theoretical model underlying it. Secondly, we use an example (matrix multiplication algorithm) to illustrate all the method steps, which are: Algorithm Choice-Criteria, Problem Presentation (how to present the problem to the student), Modelling the algorithm (using the theoretical model), Programming (using an appropriate parallel language), Functional Simulation of the program, Behavioral Simulation (algorithm and architecture), and Trace Visualization and Evaluation. This paper gives a description of the parallel systems development method, based on our own experience with PSEE (Parallel System Evaluation Environment) [1].

We describe the structure and operational mode of a coprocessor system which, when incorporated in a microprogrammed syetem to carry out Dynamic Vertical Migration, improves execution speed for any program. The coprocessor includes an interconnection mechanism between the machine code and the instruction set microcode. The interconnections (Intermediate instructions) are created in parallel with machine instruction execution and so do not increase normal execution time. This intermediate code is stored dynamically in coprocessor memory, saving the fetching and decoding phases in subsequent executions, speeding up the execution of repetitive machine code.The coprocessor structure is organized around three basic elements: Interconnection Memory, Interconnection Memory Management Unit and Coprocessor Control Unit. A software simulator has been developed to analyse coprocessor behaviour and a theoretical model has been formulated from the results ot these analyses.

PSEE (Parallel System Evaluation Environment) is a software tool that provides a multiprocessor system for research into alternative architectural decisions and experimentation, with such issues as selection, design, tuning, scheduling, clustering and routing policies. PSEE facilitates simulation and performance evaluation as well as a prediction environment for the design and tuning of parallel systems. These tasks involve cycles through programming, simulation, measurement, visualization and modification of parallel system parameters. PSEE includes a parallel programming tool, a simulator for link oriented parallel systems, BOLAS, and a performance evaluation tool, GRAPH. These PSEE modules are tools oriented to support the above tasks in user-friendly, interactive and animated graphical form. PSEE provides quantitative information in a graphical tailored form. This numerical/graphical output helps the user make decisions about his/her particular development.

A method for Dynamic Vertical Migration based on the inclusion of a coprocessor is described. It optimally runs without firmware monitoring techniques and can be applied with neither knowledge of loops bounds, nor their microprogrammability. The coprocessor generates, for every instruction, an interconnection between the instruction and its microprogram execution code. This interconnections are stored in a coprocessor memory saving the fetching and decoding phases in subsequent executions. The coprocessor structure is organized around three basic elements. Interconnection Memory, Interconnection Memory Management Unit and Coprocessor Control Unit. The behaviour of the Interconnection Memory Management Unit has been studied for two different replacement algorithms.

Programs for parallel computers of distributed memory are difficult to write, understand, evaluate and debug. The design and performance evaluation of algorithms is much complex than the conventional sequential one. This short paper describes the PSEE (Parallel System Evaluation Environment), an interactive graphical environment, which permits to study the behaviour of parallel distributed memory systems. PSEE is an easy-to-use environment that enables parallel distributed memory systems programmers take decisions about the behaviour program and parallel computer in terms such as: scalability, tuning and performance of the underlying parallel machine.