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This study, to the best of authors’ knowledge, is the first to investigate the feasibility of using picosecond UV laser ablation to fabricate ultrasmall microvias scaled down to 3 $\mu \text{m}$ and less with a pitch of 8 $\mu \text{m}$ in a 5- $\mu \text{m}$ Ajinomoto buildup film (ABF). The state-of-the-art microvias are 20 $\mu \text{m}$ in diameter by a nanosecond UV laser and 5 $\mu \text{m}$ in diameter by a picosecond UV laser reported in our previous study, but microvias of less than 2 $\mu \text{m}$ in diameter are needed to meet IO density requirements for today and future’s high-bandwidth packaging and heterogeneous system integration. In this study, we have investigated the impact of laser power, beam sizes, and materials on the via size and explored the feasibility of picosecond UV laser ablation for ultrasmall microvias with an additional layer of 80-nm-thick copper on top of the dielectric as a barrier layer. The power used to fabricate the 5- $\mu \text{m}$ microvias in a 5- $\mu \text{m}$ -thick ABF could open 2- $\mu \text{m}$ holes in the copper barrier layer due to the higher ablation threshold of copper. The drilled copper layer then serves as a mask to produce smaller microvias in the dielectric layer beneath the copper. In this article, fully opened microvias of 3 $\mu \text{m}$ diameter in ABF will be demonstrated. Submicrometer openings in copper are also achieved, which suggests the feasibility to scale down via diameter to submicrometer level. [ABSTRACT FROM AUTHOR]

This article presents for the first time microvias scaled down to sub- $5~\mu \text{m}$ in diameter fabricated using picosecond UV laser ablation in a nonphotoimageable dielectric film. The motivation of this article is to address post-Moore and More-than-Moore packaging interconnect needs. Microvias play a critical role in package interconnections in IO density and the IC bump pitch for 2.5-D interposers and fan-out packages. UV laser ablation has been the key technology for fabricating small microvias in high density interconnect (HDI) packaging for more than two decades. The state-of-the-art microvia fabricated by UV laser ablation is still at $20~\mu \text{m}$ in diameter and 50 $\mu \text{m}$ in pitch. This article explores the feasibility of fabricating microvias of $5~\mu \text{m}$ or less in diameter with a commercially available picosecond UV laser system. The experimental results show that microvias of $5~\mu \text{m}$ or less in diameter in a 5- $\mu \text{m}$ -thick Ajinomoto buildup dielectric film (ABF) are achieved. This article also addresses the fundamentals of picosecond pulsed laser ablation on polymer dielectric materials and processes optimization to generate sub-5- $\mu \text{m}$ microvias. The via pitch of 8– $12~\mu \text{m}$ is demonstrated. UV laser ablation also addresses the issue of limited availability of photosensitive dielectric materials for photolithography-based microvia fabrication. [ABSTRACT FROM AUTHOR]

This paper presents the latest advances in photolithography technologies to enable scaling of package redistribution layer (RDL) toward critical dimensions (CD) of $1 ~\mu \text{m}$ and below. High-bandwidth memory channels require not only fine pitch but also low-trace-delay RDL. High-aspect-ratio (AR) traces enable lower delays, and the photolithographic advances to achieve such traces are demonstrated on panel-based glass substrates for packages with low cost, high input/output (I/O) density, high bandwidth, and large body size. CD of 0.9- $\mu \text{m}$ line and space with an AR of 5.5 was successfully demonstrated using a low-numerical aperture (NA = 0.16) $1 \times$ i-line projection stepper tool with a novel chemically amplified plating photoresist. The 1- $\mu \text{m}$ lithography technology is a must for high-density RDL to enable 2.5-D interposer and embedded fan-out package substrates. These architectures can achieve I/O densities of 500 IOs/mm/layer. The resistance of the trace with an AR of 5 is five times lower than a trace with an AR of 1. This technological advance will greatly reduce the signal propagation loss and increase the data rate of the RDL traces. The combination of high density and high data rate will greatly increase the system interconnect bandwidth. Furthermore, low-NA stepper with a large exposure area will enable the fabrication of large-body-size interposers at low cost. This paper analyzes the relationship between trace width resolution ($w$), depth of focus, and materials to conclude that it is feasible to fill the gap between semiconductor back-end-of-line and package substrate RDL technologies. The final section discusses the issues in process development of lithography for multilayer fine-line RDLs. [ABSTRACT FROM AUTHOR]

This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- \mu \textm line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 20~\mu \text{m} or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs. [ABSTRACT FROM PUBLISHER]

Rapid changes in the semiconductor industry will continue toward higher functionality that leads to higher input/outputs (I/O) counts, pushing packaging towards higher density architectures. In the next two to three years, the I/O pitch will fall within 100 \mum for area array die and 30 \mum for periphery die. That raises an important question to the packaging industry: How will the rapid shrinkage of the I/O pitch affect the package substrate for chip attaching? The answer is sub-10 micron copper line technology. Theoretical and experimental studies on the limitations of using mercury i-line ultraviolet photolithography have been carried at the Packaging Research Center at Georgia Tech. Furthermore, ultra fine copper line routing substrates are demonstrated for flip chip attaching by using semi-additive metallization process. [ABSTRACT FROM AUTHOR]