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With the rapid growth of the microelectronic packaging market, it is necessary to increase the throughput and reduce the cost of flip chip. Driven by these evolutions, a novel revolving-turret chip transferring (RTCT) technology is introduced to implement high-throughput flip chip packaging. The unnecessary time delays of packaging processes could be eliminated in the RTCT technology due to its parallel manner of motions. In order to analyze the packaging efficiency, the layout and movement sequence of the packaging system are studied, and a calculation model of packaging efficiency is proposed. Furthermore, the effects of the critical parameters (the horizontal and the vertical spacing of antennas and the maximum velocity and acceleration of the turret-type head) on packaging efficiency are investigated to search out the optimal parameters combination. To verify the performance of the RTCT technology under optimal parameters combination, two cases are implemented and compared. The results show that due to parallel motions of processes, unnecessary delays affecting the packaging efficiency have been reduced, and the packaging efficiency of ALN-9714 inlay could be more than 35k chips per hour. In addition, compared with the conventional flip chip packaging process, the RTCT technology is more effective in packaging the chips on antennas with multicolumn layout and small horizontal spacing. [ABSTRACT FROM AUTHOR]

Microelectromechanical systems (MEMS)-type double helix chip-level electrical interconnect structures are fabricated and characterized in this paper. Due to their springlike structure, double helix interconnects have the potential to provide large mechanical compliance to compensate for nonidealities, such as nonplanarity and thermal expansion mismatch between silicon chips and substrates. A double helix configuration provides for structures with a high volumetric density of conductor for enhanced current carrying capability. The fabrication process is compatible with wafer-level fabrication and packaging. Instead of using solder to form semipermanent interconnections, the double helix interconnects use pressure to make electrical connection and provide sufficiently low resistance (~35 ± 15 mΩ). Large arrays of double helix structures have been fabricated and characterized with excellent yield. The mechanical and electrical models of the structures are presented. Reworkability tests were performed and the structures show a consistent resistance over 50 remating cycles. [ABSTRACT FROM AUTHOR]

Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance (<100~m\Omega) and high compliance (>30~\mum) in dense 2-D arrays (180–180-\mum pitch). Mechanical characterization shows that individual springs operate at approximately 150-\muN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is <40~m\Omega. A daisy-chain test die consisting of 2844 contacts is assembled into flip-chip packages with 100% yield. Thermocycle and humidity testing suggest that packages with or without underfill can have stable resistance values and no glitches through over 1000 thermocycles or 6000 h of humidity. This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules. [ABSTRACT FROM AUTHOR]