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A stochastic reaction–diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), and time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation and passivation are calculated using dissociation and repassivation of trap precursors and simultaneous diffusion and/or drift of atomic, molecular, and/or ionic species. The average of multiple stochastic simulations is used to qualitatively explain the measured BTI and SILC data. The difference in BTI and SILC time kinetics, variation in SILC time kinetics across reports, and oxide thickness dependence of TDDB Weibull slope variation are also qualitatively explained.

The spatial position and energy level of the effective oxide trap in SiC DMOSFET were investigated using Trap Spectroscopy by Charge Injection and Sensing (TSCIS) method. It was found that the oxygen vacancy traps at 1.7 eV above from the valence band of SiO 2 make threshold voltage (V th ) shift under high negative gate bias stress condition. To further understanding the extracted oxide trap, the repetitive negative stress and recovery test at V G = ±40 V were executed. The results confirm that V th and subthreshold swing (SS) change were caused by the process induced pre-existed hole traps instead of the stress induced trap generation. This hole trapping also reduced the Stress Induced Leakage Current (SILC) after the negative bias stress.

The capacitance-voltage (C-V) hystereses under positive and negative stress fields were studied on molecular beam epitaxy (MBE) Si-capped Ge metal-oxide-semiconductor (MOS) capacitors to investigate pre-existing and generated shallow and deep oxide traps. Post metallization forming gas annealing (FGA) has reduced the effective oxide trap density ( $\Delta$ N eff ) of one order of magnitude, achieving values lower than the one required of sufficient reliability (target $\Delta$ N eff ~3×1010 cm−2) at an effective oxide fields (E ox ) of ~10MV/cm (i.e., larger than at operating condition). This result demonstrates the effectiveness of FGA in reducing the hole traps in the gate stack. Furthermore, the measured C-V hystereses and the stress-induced-leakage-current (SILC) under long-time stress remained extremely small, showing the superior reliability of the MBE Si-capped Ge gate stacks on Ge.

The impact of CMOS post nitridation annealing (PNA) temperature on a 40nm embedded Flash reliability is studied. Electrical characterizations of the Flash tunnel oxide are carried out on single cell. These are used to explain the better results in terms of endurance and data retention obtained on a 512kB test chip with a lower annealing temperature. This result can be linked with the decrease of nitrogen in the bulk oxide, improving oxide wear out performance against electrical stress and stress induced leakage current (SILC). The on-chip characterization is, here, an invaluable tool to show the extrinsic behavior in the memory array and apply product-like stress.

In this paper, the physical explanation of the time dependent dielectric breakdown (TDDB) power law lifetime model is successfully interpreted through the analysis of oxide trap generation in HK/IL gate stack in NMOS-FinFET technology. The experiments are performed using the stress induced leakage current (SILC) spectrum methodology. It is found that the TDDB power law model has a strong correlation to deep trap generation. Shallow traps, on the other hand, play a role in the increase of SILC behavior and also promote further deep trap formation during the gate oxide degradation. In addition, temperature dependent and recovery voltage dependent TTDB studies reveal that, the deep trap generation is responsible for the permanent damage and the formation of percolation path during the gate oxide degradation. Through the oxygen trap study, the physics of TDDB power law lifetime model can be successfully explained.

Stress Induced Leakage Current (SILC) limits the scaling of tunnel oxide of flash memory, because it increases with the decrease of the tunnel oxide thickness. Especially, anomalously large SILC that appears on the local spots can cause bit errors. We measured Q bd and SILC characteristics of the MOSFETs with the conventional and the atomically flattened SiO 2 /Si interfaces, and the impact of the micro-roughness on Q bd and SILC has been investigated. It was found that both the numbers of the defects inducing Q bd and anomalous SILC are reduced by introducing the atomically flat SiO 2 /Si interface. And the calculated excess electric field at a projecting part is approximately 5% larger than the atomically flat part by the SILC distribution and the electric field concentration simulation. It indicates that the SiO2/Si interface micro-roughness is one of the origins that induce both the anomalous SILC and early failure in dielectric breakdown, due to localized electric field concentration effect.

This paper shows how floating gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress time and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).

The structural stability and electrical performance of SiO2 grown on SiC via direct plasma-assisted oxidation were investigated. To investigate the changes in the electronic structure and electrical characteristics caused by the interfacial reaction between the SiO2 film (thickness ~5 nm) and SiC, X-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), density functional theory (DFT) calculations, and electrical measurements were performed. The SiO2 films grown via direct plasma-assisted oxidation at room temperature for 300s exhibited significantly decreased concentrations of silicon oxycarbides (SiOxCy) in the transition layer compared to that of conventionally grown (i.e., thermally grown) SiO2 films. Moreover, the plasma-assisted SiO2 films exhibited enhanced electrical characteristics, such as reduced frequency dispersion, hysteresis, and interface trap density (Dit ≈ 1011 cm−2 · eV−1). In particular, stress induced leakage current (SILC) characteristics showed that the generation of defect states can be dramatically suppressed in metal oxide semiconductor (MOS) structures with plasma-assisted oxide layer due to the formation of stable Si-O bonds and the reduced concentrations of SiOxCy species defect states in the transition layer. That is, energetically stable interfacial states of high quality SiO2 on SiC can be obtained by the controlling the formation of SiOxCy through the highly reactive direct plasma-assisted oxidation process.

A new technique by charge injection is introduced to investigate the charging effect on weak oxide in the gate stack of high-k metal gate process. The oxide with extra oxygen vacancy is more vulnerable to process charging, as verified by the correlation of Vt vs. subthreshold swing degradation, SILC spectrum, and chemical bonding state analysis using X-ray photoelectron spectroscopy (XPS) and electron energy loss spectroscopy (EELS). Degradation of pFET threshold voltage (Vt) shift by gate injection under Source/Drain (S/D) floating condition is observed, this is attributed to the oxide damage by the accelerated carriers from S/D reverse bias. The convolution of “random dopant fluctuation (RDF) + charging effect” is expected to magnify devices Vt shift, especially for those worse bit cells with high Vt as verified by the Monte-Carlo simulation. We further demonstrate that process with tighten Vt distribution, such as FinFET technology with less implant process and better charge release immunity, is less vulnerable to the charging induced Vt shift.

In this paper, the detailed TDDB models of HK/IL gate stack for N/PMOS were established through the analysis of oxide trap generation in FinFET technology. We systematically characterized gate oxide traps of HK and IL layers by AC admittance and SILC spectrum methodologies. We found that the generation of deep traps in HK layer plays the decisive role in NMOS TDDB, while the formation of deep traps in IL and HK layers are critical to PMOS TDDB. In addition, the deep traps in HK/IL gate stack were found to be highly responsible for the permanent damage during stress, such that, the physical mechanisms of HK/IL gate stack breakdown in FinFET devices can be successfully explained through the time-dependent HK and IL trap generations. From this trap studies, we demonstrated that TDDB reliability of FinFET technology can be improved through the reduction of deep traps.

The response of lightly Al-doped Ta 2 O 5 stacked films (6 nm) to constant current stress (CCS) under gate injection (current stress in the range of 1 to 30 mA/cm 2 and stressing time of 50–400 s) has been investigated. The stress creates positive oxide charge, which is assigned to oxygen vacancies but it does not affect the dielectric constant of the films. The most sensitive parameter to the stress is the leakage current. Different degradation mechanisms control the stress-induced leakage current (SILC) in dependence on both the stress conditions and the applied measurement voltage. The origin of SILC is not the same as that in pure and Ti- or Hf-containing Ta 2 O 5 . The well known charge trapping in pre-existing traps operates only at low level stress resulting in small SILC at accumulation. The new trap generation plays a key role in the SILC degradation and is the dominant mechanism controlling the SILC in lightly Al-doped Ta 2 O 5 layers.

Reliability of NAND flash memory is more interesting than that of other semiconductor devices. Program and erase of NAND flash perform by electron injection and emission to/from floating gate (FG). There are several methods of electron injection and emission. For electron injection, there are two methods, namely channel hot electron (CHE) injection and Fowler-Nordheim tunneling (FN-t) injection. Data retention is degraded by electron and hole traps in tunnel oxide. Detrapping of trapped charges in tunnel oxide is a major root cause of V t shift during the data retention test. Read disturb failure is mainly caused in the erase state after program/erase cycling stress. The stress-induced leakage current (SILC), which is generated by program/erase cycling stress, is major root cause for the read-disturb phenomena. The mechanism of erratic over program is considered to be an excess electron injection at hole trap sites in tunnel oxide.

Using the array test pattern, gate current through the tunnel oxide on the order of 10-16 A can be measured for about 1 000 000 transistors within 4 min. Because this test pattern can be fabricated by simple processes and its peripheral circuits are simple structures, the tunnel dielectric formation method and condition can be changed drastically. It was found that anomalous stress-induced leakage current (SILC) appears or disappears by applying electrical stress, and it is annealed out during a relatively high temperature measurement at 60 °C. Random telegraph signal in SILC can be observed in some transistors. These are very similar phenomena observed in Flash memory cells. We consider that, using this test pattern for the development of tunnel oxide, we can clarify the origin of anomalous SILC and promote the downscaling of tunnel oxide thickness.

The higher effective barrier height of Dy2O3 , which is around 2.32 eV calculated from the Fowler-Nordheim plot, accounts for the reduced leakage current in Dy-incorporated HfO2 n-type metal-oxide-semiconductor devices. The lower barrier height of HfO2 characterizes the increasing electron-tunneling currents enhanced by the buildup of hole charges trapped in oxide, which causes a severe increase in the stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy-incorporated HfO2 inhibits a further increase in the electron tunneling from the TaN gate, and trapped holes lessen the hole-tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO2 dielectric demonstrate the high dielectric-breakdown strength by weakening the charge trapping and the defect generation during the stress.

The behaviors of the Snapback stress in LDD NMOSFET are studied in ultra-short and ultra-thin LDD NMOSFET's. The avalanche hot holes and electrons together inject into oxide during Snapback stress, much interface states and neutral electron traps are generated. The increase of the oxide neutral electron traps can cause the increase of SILC and the appearance of soft breakdown.

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and Vh degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.

High-kappa films are currently deposited on Ge substrates to compensate the mobility loss, as Ge offers higher mobility compared with that of silicon. This paper deals with the reliability characteristics of cerium oxide films grown by molecular beam deposition on n-type Ge (100) substrates. MOS capacitors with Pt gate electrodes were subjected to constant voltage stress conditions at accumulation. The correlation of the charge-trapping characteristics and the stress-induced leakage current (SILC) to the applied field is observed and analyzed. The results suggest that one major problem for the potential use of rare earth oxides in future MOS technology is the existence of relaxation effects. The cross-sectional value of the bulk oxide traps is on the order of 10-18 cm2 , thus indicating neutral defects. Direct comparison to reported results on high- kappa/Si and SiO2/Si structures shows that SILC properties are related to the quality of the dielectric layers; the semiconductor substrate is immaterial.

In the present work we study reliability issues of Pt/HfO 2 /Dy 2 O 3 /n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge ( Q inj ) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

In this paper we fabricated and measured the 0.26㎛ NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

The effects of the interface defects on the gate leakage current have been numerically modeled. The results demonstrate that the shallow and deep traps have different effects on the dependence relation of the stress-induced leakage current on the oxide electric field in the regime of direct tunneling, whereas both traps keep the same dependence relation in the regime of Fowler–Nordheim tunneling. The results also shows that the stress-induced leakage current will be the largest at a moderate oxide voltage for the electron interface traps but it increases with the decreasing oxide voltage for the hole interface traps. The results illustrate that the stress-induced leakage current strongly depends on the location of the electron interface traps but it weakly depends on the location of the hole interface traps. The increase in the gate leakage current caused by the electron interface traps can predict the increase, then decrease in the stress-induced leakage current, with decreasing oxide thickness, which is observed experimentally. And the electron interface trap level will have a large effect on the peak height and position.

The stress effect of SiGe pMOSFETs has been investigated to understand the electrical properties of devices fabricated on the Si bulk and PD SOI substrates. A comparison of the drain saturation current ( I D.sat ) and maximum transconductance ( g m,max ) in both the SiGe bulk and the SiGe PD SOI devices clearly shows that the SiGe PD SOI is more immune from hot-carriers than the SiGe bulk. The stress-induced leakage current (SILC) is hardly detectable in ultra-thin oxide, because the increasing contribution of direct tunneling is comparable to the trap-assisted component. The SiGe PD SOI revealed degraded properties being mainly associated with the detrimental silicon–oxide interface states of the SOI structure.

In this study, the characteristics of Ta/chemical SiO2/Si devices with their chemical oxides formed by various chemicals, including HNO3, SC1, and H2SO4+H2O2 solutions, were first investigated. We found the HNO3 split depicts the lowest leakage current and the best hysteresis behavior. Next, chemical oxide formed by HNO3 was applied to form the interfacial SiO2 layer for metal–oxide–semiconductor (MOS) devices with Ta/HfAlO/chemical SiO2/Si structrue. The effects of a high-temperature spike anneal were then studied. We found that the spike-anneal process can effectively reduce the thickness of the chemical oxide from 10 to 7 A, thus is beneficial in preserving the low effective oxide thickness (EOT) of the structure. Furthermore, both the gate leakage current and stress-induced leakage current (SILC) were also effectively suppressed by the high-temperature spike-anneal.

The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8 nm SiO2 tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2 V.

In this paper, we report the electrical characteristics and reliability studies on tunnel oxides fabricated by "wet N2O" oxidation of silicon in an ambient of water vapor and N2O at a furnace temperature of 800 degC. Tunnel oxides that have an equivalent oxide thickness of 67 A are subjected to a constant-current stress (CCS) amount of -100 mA/cm2 using a MOS capacitor to obtain information on stress-induced leakage current (SILC), interface, and bulk trap generation. The obtained results clearly demonstrate the superior performance features of the present tunnel oxides with reduced SILC, lower trap generation, minimum change in gate voltage, and higher charge-to-breakdown during CCS studies. X-ray photoelectron spectroscopy depth profile studies of the tunnel oxide interfaces have shown that the improved performance characteristics and reliability can be attributed to the incorporation of about 8.5% nitrogen at the oxide-silicon interface of the samples formed by the "wet N2O" process that involves low-temperature oxidation and annealing at 800 degC.

Stress induced leakage currents (SILC) remain one of the main reliability problems preventing further SiO2 tunnel oxide thickness reduction in floating thin oxide (FLOTOX) memory devices. In this work, we present ultra-low level SILC current–voltage (I–V) measurements performed by using the floating gate technique on 7–8 nm thick SiO2 tunnel oxides and low-level measurements performed by direct technique measurements. Experimental characteristics obtained by the indirect measurement technique reached current levels as low as 2 × 10−17 A. They exhibit new phenomena such as negative differential resistance behavior and current threshold voltages. A physical one-step tunneling model (A-mode), taking into account the influence of defects located in the bulk SiO2, is proposed. Both spatial and energetical defect profiles are extracted from experimental data. We show that the new phenomena experimentally observed can be interpreted as a one step trap-assisted tunneling mechanism via defects located near the middle oxide, even for highly stressed components.

The defect density of the oxides used in non-volatile memories (NVM) is a key parameter to the understanding of the data loss of these structures. One of the most critical phenomena responsible for this loss (in the range of oxide thicknesses used in NVM devices) is the stress induced leakage current (SILC). The origin of SILC is generally attributed to the trap assisted tunnelling (TAT); therefore, a better understanding of the evolution of the oxide defects is necessary. It is known that the leakage through the oxide defects is temperature accelerated below 100 °C. Besides, it was observed that above 100 °C, the oxide defects are annealed. To better understand the temperature behavior of the defect population, a dedicated method has been devised and applied to several baking experiments. It leads to new observations and to the correction of some biased interpretations due to unsuitable experimental methods. Indeed, in this paper, we point out the fact that the annealing effect already occurs at 60 °C. The activation energy was calculated and found independent from both the electrical field across the oxide and the number of program/erase (P/E) cycles. The temperature behavior of the leakage is found to be more complex than what was reported in the literature: it is a balance between two opposite phenomena. Based on that, a new model describing the defect population evolution is proposed.

Reliability issues of MOSFETs such as bias temperature instability (BTI), random telegraph noise (RTN), and stress-induced leakage current (SILC), are linked to the trapping of charges in oxides. Even though the chemical structure of these oxide defects is still the subject of debate, detailed studies of these reliability phenomena have shown that their physical behavior can be successfully described by non-radiative multi-phonon (NMP) theory. In this work we characterize and study a pMOS high-k FinFET technology starting from degradation measurements up to the simulation of the energy barriers in the framework of NMP theory. This allows to investigate the aforementioned reliability issues all based on their common cause, the microscopic oxide defects.

A new oxidation scheme, namely, 'Wet N2O process' for the fabrication of tunnel oxide for flash memory applications has been developed and characterized using both aluminum gate MOS capacitors as well as poly gate MOS capacitors. The Al gate MOS capacitors were electrically characterized under constant field stress conditions for studying reliability and interface properties of the Wet N2O oxide. The poly gate MOS capacitors are electrically characterized and the Stress Induced Leakage Current (SILC) of poly gate MOS capacitors were studied under constant current stress. The results obtained show that the 'Wet N2O oxide' gives excellent interface characteristics and reliability compared to other oxides. The poly gate MOS capacitors show stability and J-E characteristics with extended Fowler-Nordheim region, high breakdown strength and extremely low SLIC when stressed with 35C/cm2 and therefore ideally suited for application in flash memory devices with tunnel oxides in the nanometer thickness range of 6 nm to 7 nm. Copyright � 2006 by the IETE.

Stress-induced leakage current and time-dependent dielectric breakdown were investigated to examine the reliability of gate oxides grown on hydrogen- and deuterium-implanted silicon substrates. An order of magnitude improvement in charge-to-breakdown was observed for the deuterium-implanted devices as compared with the hydrogen-implanted ones. Such reliability improvement may be explained by the reduction of defects in the SiO2 and Si/SiO2 interface, such as Si dangling bonds, weak Si-Si bonds, and strained Si-O bonds due to the retention of implanted deuterium at the interface and in the bulk oxide as confirmed by secondary ion mass spectroscopy

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.

Conduction behaviour of n-MOSFET capacitors with an oxide thickness (Tox) of 18.5 A was investigated before and after constant current stress. It was found that stress-induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analysed systematically, based on the assumption that the LV-SILC is due to interface trap-assisted tunnelling (ITAT) process. Using the LV-SILC as a probe, the generation of interface defects was probed by the LV-SILC. Interface defects in both anode and cathode are involved in the ITAT process, but the former dominates the oxide reliability. Based on the results of interface defect generation sensed by the LV-SILC, a new method to project lifetime (TBD) or monitor the oxide reliability was set up.

The conduction mechanism of stress induced leakage current (SILC) through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress (CVS). The simulation results show that the SILC is formed by trap-assisted tunnelling (TAT) process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.

This work presents the border trap generation characteristics in 8.5nm thick nitrided gate oxides for positive and negative Fowler-Nordheim stress polarities. These traps are located around a distance of ~2.3nm from either oxide interfaces and can be charged/discharged by direct tunneling. The gate-side and substrate-side border trap densities, determined for different stress levels by the combination of transient SILC and transient capacitance measurements, agreed well with hysteresis measurements in C-V experiments. It was found that in nitrided gate oxides the substrate-side border trap generation is strongly dependent on the stress polarity while the gate-side trap generation appeared polarity independent.

In this work we present two analytical (and physically supported) models to describe trap kinetics in both thin and ultra-thin SiO2 films. The models are based on the different mechanism controlling the carrier transport through the oxides and on the assumption of a two step process for creating stable traps, through defect precursors. Experimental data of stress induced leakage current confirm the validity of models predictions. Furthermore, a systematic study of the transient of trap kinetics experimentally demonstrates the existence of defect precursors as well as a reduction of oxide damage under pulsed stress condition respect to DC case.

International audience; The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunneling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by VG and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunneling.

Homeotropically oriented nematic liquid crystals (NLC) have been used for visualization of different types of electrically active defects (EAD) in Si–SiO2 structures with thin (3–7 nm) oxides thermally grown on silicon. Optical images of defects revealed by the NLC method have been investigated depending on applied voltage and its polarity. Possible local properties of EAD have been studied by intentional introduction of some types of non-uniformities in Si–SiO2 structures. Selective low-energy electron (5–20 keV) irradiation by means of scanning electron microscope (SEM) has been used for this purpose. Definite similarity between images of real EAD and locally irradiated regions have been found. Possible nature of this phenomenon and peculiarities of EAD electrophysical properties are discussed. Local variations of fixed oxide charge and other electrophysical parameters have been revealed in EAD using direct measurements by mercury microprobe. In some points of EAD the local oxide conductivity have been found higher than outside defect. We have also shown that stress induced leakage currents (SILC) in the regions containing EAD are larger than in non-defect areas of Si–SiO2 structures. The presence of heavy (Fe, Cr) and alkaline metals was detected in defects by the secondary ion mass spectroscopy (SIMS). Thus, EAD revealed by the NLC method represent non-uniformities potentially dangerous for microelectronic devices with thin functional oxides.

The gate leakage current and reliability concern become more serious due to the aggressive scaling-down of the gate oxide thickness. In this paper, the gate leakage current reduction and reliability optimization with an EOT 15A plasma nitrided gate oxide were explored. The plasma nitrided oxide fabricated by plasma nitridation process demonstrated good gate leakage reduction and high carrier mobility without sacrificing the reliability performance. The optimization of nitrogen profile and post nitridation annealing has been also discussed.

Stress induced leakage current (SILC) has been discussed for a long time by many researchers. The oxide traps are believed to be the cause of SILC, but characterization of these traps is still not clear. In this paper, we demonstrate that the SILC related oxide traps can be distinguished into two kinds with different characterization parameter by PDO method. Linear fitting also shows that double oxide trap model is better than single oxide trap model.

The dielectric degradation of 2.6–4.9-nm-thick SiO2 has been studied by analyzing stress-induced leakage current (SILC) and soft breakdown (SBD) current under gate and substrate injections. We found a critical oxide field for the transition from the SILC mode to the SBD mode, independent of oxide thicknesses and stress polarities. The SILC and the leakage current just after SBD can be simulated well using a dielectric degradation model where the conductive path is locally extended in SiO2 from the SiO2/Si interface and the current is limited by electron tunneling through remaining undegraded SiO2 on the top of the conductive path. From the temperature dependence of the transition from the SILC mode to the SBD mode, we also found that the activation energy of the transition changes at ~150°C, which can be associated with the population of characteristic phonons in the Si–O–Si network, regardless of stress polarities.

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

A three-dimensional Monte Carlo model for analysis of the reliability of flash memory arrays is developed, and applied to thin tunnel oxide (t/sub ox/ = 5 nm) samples. Good agreement between experimental data and simulation results are obtained, assuming a correlated defect generation in the tunnel oxide of our samples as evidenced in (Ielmini et al., 2004). The impact of correlated defect generation on dielectric breakdown is also addressed by means of a percolation model. It is shown that correlated generation provides no significant degradation of the breakdown lifetime with respect to Poisson statistics.

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.

To support the International Technology Roadmap for Semiconductors, equivalent thickness of the gate dielectric will need to be 1.0-1.5 nm by 2004. Due to increased power consumption, intrinsic device reliability, and circuit instabilities associated with SiO2 of this thickness, a high-permittivity gate dielectric (e.g., Si3N4, HfSixOy, ZrO2) with low leakage current and at least equivalent capacitance, performance, and reliability will be required. In this work, we investigate the stress-induced leakage current (SILC) at low field for both PMOS and NMOS with ultra-thin nitrided gate oxide with thickness of 1.6 nm. C-V measurements are used to extract the oxide thickness (Tox) and the substrate doping (Np), which must be corrected for this range of oxide thickness. The SILC generation kinetics after constant voltage stress is shown to be related to that of interface or near-interface oxide traps and to the concentration of the atoms of nitrogen near to the interface. Moreover, the situation in PMOS is just contrary to the NMOS. We attribute this to the different barrier lowering in conduction band and valence band.

This work presents a detailed investigation of the local transient tunneling currents due to substrate- and gate-near traps generated by Fowler-Nordheim stress in nitrided oxide MOS structures. We demonstrate that for the correct interpretation of the transient stress-induced leakage currents measured in the external circuit, it is essential to include the effects of the substrate and poly-Si capacitances. This leads to gate-voltage-dependent weighting factors, which relate the measured current transients to the local trap tunnel currents near the substrate and the gate. By a combination of these measurements with transient capacitance measurements, it is possible to separately determine the local tunnel currents and, thus, the densities of traps generated close to the substrate and to the gate.

Ultra-thin gate oxides with thickness smaller than 3 nm were prepared by anodic oxidation (anodization) in deionized water under direct-current biasing superimposed with alternating-current signal (DAC-ANO). It is experimentally observed that the DAC-ANO oxides after suitable high temperature annealing have better electrical characteristics than conventional rapid thermal oxides (RTO). Other advantages of DAC-ANO oxides include lower leakage current, higher time-zero dielectric breakdown and time-dependent dielectric breakdown endurance, and less stress-induced leakage current. The charge trapping behavior under high field stress is less significant in DAC-ANO oxides than in RTO ones. The improved reliability of DAC-ANO oxides can be explained by the nature of AC switching effect. DAC-ANO oxide is a potential candidate in the application of ultra-thin gate oxide to deep sub-micron devices.

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10-3/ . The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

Thin films of silicon dioxide are deposited on ZnO/n-Si substrate at a low temperature using tetra-ethylorthosilicate (TEOS). The ZnO/n-Si films have been characterized by atomic force microscopy (AFM) and scanning electron microscopy (SEM). The border trap density (Qbt) and fixed oxide charge density (Qf/q) of the SiO2/ZnO/n-Si films are found to be 3.9 × 1010 cm−2 and 1.048 × 1011 cm−2, respectively. The trapping characteristics and stress induced leakage current (SILC) have also been studied under Fowler-Nordheim (F-N) constant current stressing.

This paper investigates the use of Fowler-Nordheim tunneling for Flash memories programming looking for a good tradeoff between applied voltage (to relax requirements for on-chip circuitry), program time and oxide stress-induced leakage current (SILC) degradation. Exploiting the results of a recent study of trap dynamics under pulsed tunnel conditions, it is shown that by means of a small number of relatively high voltage pulses, memories featuring oxide thickness of 7 nm can be programmed in about 20 /spl mu/s with smaller SILC degradation than commonly achieved with programming times in the ms range.

In this paper, we report on the effect of deuterated poly-Si deposition on stress-induced leakage current (SILC) under Fowler–Nordheim (F–N) electron injection. A deuterated poly-Si gate electrode was deposited on wet and dry thin gate oxide films by utilizing deuterated monosilane (SiD4) gas, as a substitute for hydrogenated monosilane (SiH4) gas. As a result, it was found that SILC values of both wet and dry oxides were clearly suppressed by the deuterated poly-Si gate electrode. Experimental results for the depth profiles of the introduced-deuterium atoms indicated that a large amount of deuterium is introduced into the gate oxide films after the deuterated poly-Si deposition. Furthermore, it was found that hydrogen concentration in a wet oxide film decreases by high-temperature deuterium annealing, while deuterium concentration increases. It is inferred that both high concentration of deuterium and high-temperature annealing for gate doping after poly-Si deposition bring about the suppression of SILC due to the efficient replacement of hydrogen with deuterium in gate oxide films.