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Gallium nitride (GaN) field-effect transistors have low ON resistance and switching losses in high-frequency (>MHz) resonant wireless power transfer systems. Nevertheless, their performance in the system is determined by their characteristics and operation mode. A particular operating mode in a 6.78-MHz magnetic resonant wireless transfer system that employs class-D GaN power amplifiers in the zero-voltage switching mode is studied. Two operation modes, the forward mode and the reverse mode, are investigated. The nonideal effect under the device-level dynamic resistance and thermal effect are also analyzed. The dynamic resistance under different operation modes is demonstrated to have different generation mechanisms. Finally, the device characteristics with system operating conditions are combined, and the effects of temperature and dynamic resistance under different operating conditions are evaluated.

Dynamic ON resistance of GaN devices is a must-care point for users. In this paper, the reverse conduction of commercial GaN power transistors is studied. Even though the commercial HEMTs show stable performance in normal operation modes (off-to-on), significant dynamic ON resistance can be seen in some particular conditions. A test method is set up to evaluate dynamic Ron in a reverse-to-on mode. The conditions to activate the behavior are discussed, and the cause of dynamic Ron is possibly due to traps located in the gate region. Meanwhile, a wireless power transfer system operating at 6.78MHz is used to study the effect of reverse conduction mode on dynamic resistance at the circuit level. According to the change of the operation frequency, we find that the influence of reverse conduction on the dynamic Ron effect is not only affected by the value of reverse conduction voltage but also related to the operating mode of the device.

In this paper, a novel method to achieve all-GaN integrated MIS-HEMTs in a Si-CMOS platform by self-terminated and self-alignment process is reported. Furthermore, a process of repairing interface defects by supercritical technology is proposed to suppress the threshold voltage shift of all GaN integrated MIS-HEMTs. The threshold voltage characteristics of all-GaN integrated MIS-HEMTs are simulated and analyzed. We found that supercritical NH3 fluid has the characteristics of both liquid NH3 and gaseous NH3 simultaneously, i.e., high penetration and high solubility, which penetrate the packaging of MIS-HEMTs. In addition, NH2− produced via the auto coupling ionization of NH3 has strong nucleophilic ability, and is able to fill nitrogen vacancies near the GaN surface created by high temperature process. The fabricated device delivers a threshold voltage of 2.67 V. After supercritical fluid treatment, the threshold voltage shift is reduced from 0.67 V to 0.13 V. Our demonstration of the supercritical technology to repair defects of wide-bandgap family of semiconductors may bring about great changes in the field of device fabrication.

All-GaN cascode devices were realized by integrating the GaN MIS-FET and MIS-HEMT on wafer by self-terminated and self-alignment process. Thus, only one additional mask was needed compared with the single-GaN devices for the recess gate patterned. The fabricated device delivers a threshold voltage $(V_{th})$ of 3.6 V. The hysteresis $(\Delta V_{th})$ is 0.6 V and the hard breakdown is observed at 883V.

Reverse conduction of commercial GaN high electron mobility transistors (HEMT) for power applications, is found to induce significant dynamic ON resistance in some particular conditions, even though the commercial HEMTs show stable performance in normal operation modes. A test method is set up to evaluate dynamic Ron in this special mode. The conditions to activate the behavior are discussed. The cause of dynamic resistance is possibly due to traps located in gate region.

This paper presents a high-accuracy complementary metal oxide semiconductor (CMOS) driven ultrasonic ranging system based on air coupled aluminum nitride (AlN) based piezoelectric micromachined ultrasonic transducers (PMUTs) using time of flight (TOF). The mode shape and the time-frequency characteristics of PMUTs are simulated and analyzed. Two pieces of PMUTs with a frequency of 97 kHz and 96 kHz are applied. One is used to transmit and the other is used to receive ultrasonic waves. The Time to Digital Converter circuit (TDC), correlating the clock frequency with sound velocity, is utilized for range finding via TOF calculated from the system clock cycle. An application specific integrated circuit (ASIC) chip is designed and fabricated on a 0.18 μm CMOS process to acquire data from the PMUT. Compared to state of the art, the developed ranging system features a wide range and high accuracy, which allows to measure the range of 50 cm with an average error of 0.63 mm. AlN based PMUT is a promising candidate for an integrated portable ranging system.

In this paper, we design and fabricate a radio frequency (RF) signal transmission structure for a 3D stacked structure. Usually, this structure uses co-planar waveguide (CPW) and Through Silicon Via (TSV) to realize the horizontal and vertical RF signal transmission on the same interposer respectively. With the help of micro-bump, we can transport RF signal in a stacked structure. Furtherly, we design and fabricate a patch antenna with a stacked structure, fed by the structure we proposed. Through the measurement of the antenna, we determine the effectiveness of this transmission structure.

This paper proposes a vertical coaxial transmission structure made of a centered Cu TSV surrounded with a cycle of TSVs as grounding shield. To verify the feasibility, a set of vertical coaxial transmission structure linked with CPW lines is designed to be able to work at 40GHz and parametric study is conducted in the meantime. By changing the diameter of the grounded TSV ring array and the space of centered RF TSVs, the results show that test structures have good high frequency transmission performance; the larger the diameter of the grounded TSV ring array, the better the transmission performance; the S21 parameter does not change significantly when the space between the two centered RF TSVs is changed. With developed TSV process, sample is fabricated and tested. The insertion loss is less than 1.2dB@40 GHz for the two vertical coaxial transmissions structures linked with CPW lines, and it can be derived that it has a less than 0.15dB@40GHz for a single coaxial transmissions structure.

In this study, we present a Q-band patch antenna with an underling cavity integrated on the stacked high-resistivity Si interposers. A process is developed and sample is fabricated. Evaluation is done and the measurement results shows that it has an operating frequency of 32.75GHz, a –10dB bandwidth of 1.04GHz, a maximum gain of 3dB. Those results prove the feasibility of integrating high-frequency antennas with TSV interposer preliminary.

The great advances in silicon photonic sensing technology have made it an attractive platform for a wide of sensing applications. However, most silicon photonic sensing platforms suffer from high susceptibility to the temperature fluctuation of operating environment. Additional complex and costly chemical signal enhancement strategies are usually required to improve the signal-to-noise ratio (SNR). Here, a biotoxoid photonic sensor that is resistant to temperature fluctuation have been demonstrated. This novel sensor consists of a ring resonator coupled to a Mach-Zehnder interferometer (MZI) readout unit. Instead of using costly wavelength interrogation, our photonic sensor directly measures the light intensity ratio between the two output ports of MZI. The temperature dependence (TD) controlling section of the MZI is used to eliminate the adverse effects of ambient temperature fluctuation. The simulation and experimental results show a linear relationship between the interrogation function and the concentration of analyte under operation conditions. The thermal drift of the proposed sensor is just 0.18%, which is a reduction of 567 folds for chemical sensing and 28 folds for immuno-biosensing compared to conventional single ring resonator. The SNR increases from 6.85 dB to 19.88 dB within a 2°C temperature variation. The high SNR optical sensor promises great potential for amplification-free of detection of nucleic acids and other biomarkers. Ministry of Education (MOE) National Research Foundation (NRF) Accepted version

In this study, we investigated the effects of the electrode area and interval on bilateral silicon detectors in order to improve the neutron dose sensitivity while also considering the current density. The voltage–current and sensitivity–current characteristics of PIN diodes were measured experimentally. Detectors were fabricated with different electrode intervals and electrode areas, and the effects of these structural parameters on the detector sensitivity were investigated. We found that the sensitivity at 1.0 mA could be improved to 1170 mV/Gy by using an electrode interval of 4000 μm and an electrode length of 600 μm. Thus, we demonstrated the feasibility of achieving high sensitivity with a thin detector.

This paper presents the fabrication and characterization of a low parasitic capacitance and low-stress Si interposer for 2.5-D/3-D integration of stress sensitive MEMS devices. The glass reflow process is utilized to isolate Si posts (through silicon interposer) from Si substrate of a low resistivity to form vertical electrical interconnection. A process is developed and a dummy Si interposer is fabricated. Using the fabricated samples, the Si interposer is characterized in terms of resistance, parasitic capacitance, breakdown voltage, and residue stress test. Air-gapped Si interconnection is measured with a resistance of 0.9 ${\Omega }$ , a parasitic capacitance of 85.12 fF and a breakdown voltage of 250 V at least. The residual stress of Si interposer is also investigated through infrared flare technology and shows a result that less than 30 MPa around the Si interconnection at 350 °C.

This paper develops an annular copper through silicon via (TSV) integration process. Additives, including accelerator, suppressor, and leveler, with different concentrations are employed in the methanesulfonic-based electrolyte. Besides, other influence factors, including current density, forced convection, and environment temperature, are also taken into consideration for the sake of annular TSV filling. A same number of samples with annular and fully filled copper TSV, in the same structure parameters and technological conditions, are fabricated, respectively. Electroplating experiment, X-ray inspection, electrical testing as well as reliability testing are performed in order to compare the characterization of the two integration processes. All test results support this proposed annular TSV integration approach has great application prospect for passive interposer applications.

The conventional monolithic integration of silicon PIN detector as △E-E telescope suffer from incompatibility with IC process, signal crosstalk, high cost, etc.. In this paper, integrated silicon PIN detector based on Al-Sn-Al bonding is proposed. The intermediate conductive layer between thin and thick PIN structure comprises of metallic bonding layer, which can reduce the signal crosstalk. Moreover, the novel integration process enables known-good-die (KGD) bonding of thin and thick PIN structure, which increases flexibility and reliability of the fabrication process. Besides, the fabrication reduces the cost and increases reliability by utilizing silicon integrated process.

In this paper, radiation reliability of through-silicon via (TSV) was studied experimentally. Characterization of leakage current between adjacent TSVs and capacitance of an array of TSVs was used to evaluate the effects of radiation on reliability of TSVs. All samples were exposed to 60Co ${\gamma }$ radiation with a total radiation dose of 500 Gy. It was observed that leakage current increased and coupling capacitance decreased. The increase of leakage current was explained based on the percolation model for thin oxide layers. The decrease of capacitance was analyzed with the theory of coupling capacitance and equation of flat-band voltage and charge in the oxide layer. It is important and necessary to consider the effect of radiation on reliability of TSV for TSV-based applications under radiation conditions.

For devices with a 15 micron anode-to-cathode distance, nearly 1.5 times increase in the blocking (breakdown) voltage (from 692 to 1030 V) has been achieved by replacing the alloyed Ohmic contact at the anode electrode of the conventional MOS gated hybrid-anode lateral field-effect rectifier (CMLFER) with a low barrier Schottky contact. The new Schottky-MOS hybrid-anode lateral field-effect rectifier is found to offer comparable low onset voltage ( ${V}_{{\textbf {ON}}}$ of 0.68±0.13 versus 0.65±0.11 V for CMLFER) independent of the anode-to- cathode distance. The immunity of the punch through caused by drain induced barrier lowering effect is obtained through the low barrier Schottky contact in anode, which is believed to be responsible for the reduction in the leakage current, and the improvement of rectifier breakdown voltage.

This paper proposed a three-dimensional integrated RF transceiver module based on high resistivity Si interposer embedded with microchannel for on-site heat dissipation. It's composed of three stacked layers of TSV interposer, including the bottom one embedded with microchannels for on-site cooling which has four high power chips assembled on its top side, the middle one having four large cavities to accommodate the chips assembled on the bottom one which is utilized as a supporting layer, the top one having a IC driver chip mounted on its top side. In order to study its thermal property, a simplified thermal resistance network is built and analysis is done. To validate this method, finite element simulation is conducted and the results show that maximum deviation of the temperature rise of each high power chip mounted on the bottom Si interposer referring to coolant is 9.04% and minimum deviation is 4.85% in the range from 0.1m/s to 1m/s for DI coolant.

In the past 60 years, integrated circuits have been developing in the direction of smaller size and higher integration under the guidance of Moore's law. However, the heat dissipation problem of the chip becomes prominent as the chip size decreases and the integration degree increases. Therefore, this paper presents a manifold microchannel interposer based on advanced packaging technology. Compared with traditional heat sink, the interposer has high heat dissipation performance, low flow resistance, strong compatibility with IC and small thickness. The micro-channel structure of the heat sink optimized by COMSOL™ simulation software and fabricated by etching, photolithography, silicon-silicon direct bonding, thin polishing and other microelectromechanical systems (MEMS). A stable and reliable thermal testing system is designed and tested for the thermal testing of heat sink. The test results show that when the input flow rate is 40 ml/min, the heat dissipation capacity can reaches 550 W/cm2, and the chip surface temperature is only 128 □.

A new real-time compensation method of threshold voltage (Vth) and mobility (μ) for large size AMOLED display named ‘linear charging sensing (LCS)’ is proposed in this paper. This compensation method can accomplish the Vth and μ sensing within tens or hundreds microseconds which can realize the sensing for all the pixels of FHD (1920×1080) AMOLED display within one frame time. By simulation analysis, LCS compensation method is found to have high accuracy for V th sensing with an error of 0.07V for ΔV th =0.5V and no error for ΔV th =-0.5V. Verified in FHD AMOLED panel further, the proposed method improves image sticking and luminance uniformity significantly.

In this paper, we reported a supercritical treatment technology to suppress the positive shift in threshold voltage. After treatment, threshold voltage shift ($\triangle$ V th ) under forward gate bias stress decreased from 4.05V to 0.15V, gate leakage current was reduced from 10-9mA/mm to 10-11mA/mm. It was suggested that nitrogen ions could modify interface state traps with a broad distribution of trapping, leading to suppressed gate leakage current and threshold voltage drifts.

With semiconductor processes advancing, integrated circuits have moved further along the Moore's Law [1]. Meanwhile, chip integration and power density increased substantially, making thermal problems more serious [2]. In this circumstance, researchers have conducted a large number of experiments on fluid flow and heat transfer in microchannels, to improve cooling performance. In the early days, microchannel heat dissipation technique was mostly achieved by etching microchannels on silicon wafers. There is no doubt that diamond has a thermal conductivity one magnitude higher than silicon. So diamond can improve the heat dissipation performance of the heat sink. Due to diamond etching technology has been developed, the use of diamond as a material for heat sinks has received extensive attention. In this paper, finite element simulation is used to study thermal property of diamond heat sink. The microchannel heat sink is fabricated by bonding a diamond wafer and a silicon wafer. Temperature rise is the objective function to be minimized with height of microchannels (H c ), number of microchannels (N), and the duty ratio of microchannel (α), as optimize variables. Depending on the experimental results, combined with the actual feasibility, the best result is that the flow path height is 250 μm, the duty ratio is 0.7, and the number of flow channels is 60. Under this condition, the temperature rise is 30°C.

In this paper, we present a TSV interposer integrated X-band microstrip filter. It designed as working at X band with an insertion loss (IL) of 2.2dB, measuring 2.8mm×3.7mm in size. With processed sample, the measured bandwidth (BW) is about 2.33GHz, the passband insertion loss is about 2.2dB.

Leakage current between through-silicon vias (TSVs) and surrounding silicon substrates is a critical electrical reliability problem. Many works have been reported, including factors affecting leakage current, methods to reduce leakage current, leakage current paths and evaluation of TSV yield through leakage current measurement. However, influence of measurement condition or measurement method itself on TSV leakage current was seldom studied in previous works. In this paper, TSV samples with thermal oxidation SiO2 layer and TSV samples with inductively coupled plasma chemical vapor deposition (ICPCVD) deposited SiO2 layers were fabricated and their I-V characteristics of leakage current were measured and compared. Different measurement methods were applied by changing sweeping voltage increments, voltage polarities and single or double sweeping modes. For TSV samples with thermal oxidation SiO2 layers, measured TSV leakage current at 20 V was in the order of 10-12 A and its detailed numerical value increases with sweeping voltage increments. A hysteresis curve was observed as double sweeping mode was applied due to effect of SiO2 layers capacitors charge and discharge processes. TSV samples with ICPCVD deposited SiO2 layers are very leaky and measured leakage current at 20 V was in the order of hundreds of 10-9 A. The influence of sweeping voltage increments and sweeping modes can be neglected for such samples. In conclusion, measurement setup and measurement parameters are important factors to evaluate TSV leakage current. It is important to understand the influence of measurement conditions on the leakage current in TSVs.

This paper mainly designed an aluminum nitride based piezoelectric micro-machined ultrasonic transducer (AlN PMUT) as a wireless power receiver. AlN PMUT is a stacked layers structure of Si/SiO_2/Mo/AlN/Al about 4µm/1µm/0.1µm/2µm/1µm in thickness from bottom to up suspended by a cavity measuring in 0.496mm×0.506mm. Fabrication and characterization are conducted as a wireless power receiver. According to the wireless power transmission experiment, AlN PMUT can generate a peak voltage about 38.6mV when it receives an input sonic wave with a sound pressure of 2×10^4Pa.

A fine-pitch through-silicon via integration approach with self-aligned back-side benzocyclobutene passivation layer is proposed. Different from the conventional lithographic process, the passivation layer is realised by leveraging plasma etching and chemical-mechanical polishing process. With its well-controlled repeatability, this approach can help reduce the process defect and copper contamination. A plenty of measurement techniques including X-ray radiographic testing, optical and scanning electron microscope observation, four-probe electrical measurement, as well as vector network analyser, are employed in order to verify the fabrication quality and the electrical performances. All the test results support that this fine-pitch through-silicon via integration approach has a promising application prospect.

In this paper, a low-cost through-multilayer TSV integration process has been developed. The features are that a double-layer spin coating technique is applied to prevent residual photoresist left inside TSVs. Besides, redistribution layer is deposited before TSV filling in order to eliminate the front-side chemical-mechanical planarization process, which will lower the fabrication cost. Basic electrical tests of single layer chip are performed in order to pick out these known good dies for stacking. A given mass of stacking TSV integration samples are fabricated. Electrical test results are presented to show the quality of TSV interconnects and TSV isolation. The quality of bonding strength is characterized through shear tests, and the optimized bonding parameters are put forward after a set of experiments with different parameter combinations. The mean of bonding precision is $3.31~{\mu }\text{m}$ , with the bonding yield being 94.17%. Thermodynamic simulation is simulated to characterize the stress and warping values of this multi-layers TSV integration. All test results support the good quality of this through-multilayer integration approach.

Measurement-based electrical characterization of through silicon via (TSV) and redistribution layer (RDL) is of great importance for both fabrication process and system design of 3D integration. This paper presents the electrical measurements and analysis of TSV and double-sided RDL test structures, from DC to high frequency up to 40GHz. TSV shows great dependence of DC resistance and leakage current on fabrication process. An inverse V-shaped C-V curve is presented between adjacent TSVs in N-type silicon substrate, from -10V to 10V. In the high frequency characterization, two methods are proposed and applied to extract resistance and inductance of a single grounded TSV. Individual transmission loss of TSV, RDLs on top and bottom surface of silicon substrate are calculated, and corresponding circuit parameters thereof are extracted to characterize their electrical properties precisely. Display Omitted Measure TSVs and metal lines at DC and high frequency up to 40GHzApply two methods to extract resistance and inductance of single TSVSeparate individual transmission loss of TSV and metal line from test structuresExtract circuit parameters of TSV and metal lines up to 40GHz

The impact of supercritical CO2/H2O technology on the threshold-voltage instability of AlGaN/GaN metal-insulator semiconductor high-electron-mobility transistors (MIS-HEMTs) is investigated. The MIS-HEMTs were placed in a supercritical fluid system chamber at 150 °C for 3 h. The chamber was injected with CO2 and H2O at pressure of 3000 psi (1 psi ≈ 6.895 kPa). Supercritical H2O fluid has the characteristics of liquid H2O and gaseous H2O at the same time, that is, high penetration and high solubility. In addition, OH− produced by ionization of H2O can fill the nitrogen vacancy near the Si3N4/GaN/AlGaN interface caused by high temperature process. After supercritical CO2/H2O treatment, the threshold voltage shift is reduced from 1 V to 0.3 V. The result shows that the threshold voltage shift of MIS-HEMTs could be suppressed by supercritical CO2/H2O treatment.

Transmitter/Receiver (T/R) is a basic part for the RF front-end module, whose miniaturization and integration are very important for the improvement in integration density, function complexity and performance. The state of art of high performance T/R is mainly realized with heterogeneous integration based on advance ceramics such as High Temperature Co-fired Ceramic (HTCC) and Low Temperature Co-fired Ceramic (LTCC). This scheme is helpful to fully utilize the excellent performance of various devices based on substrate such as GaAs, InP, and GaN substrate, however, it confronts shortcomings in re-wiring lines of low precision, shrinkage mismatch during co-firing process, low thermal conductivity. TSV interposer having its Re-wiring line realized with IC back-end metallization process, MEMS process, etc., and using Through-Silicon-Via (TSV) to achieve vertical interconnections between rewiring lines on both surface, is able to provide a good match in rewiring line with RF microelectronic chips, factoring in improvement in RF loss properties with high-resistivity Si as substrate instead of normal low resistivity Si, therefore is acknowledged to be a competitive package substrate for building a highly integrated RF system. In this context, we present a 2.5D integrated L-band Receiver based on TSV interposer, the test results prove the feasibility of 2.5D RF integration enabled by high-resistivity Si interposer.

As the growing demand for high power and high -density RF device integration, the system faces a serious thermal challenge. Microfluidic cooling has emerged as an effective method for heat dissipation inside electronic devices. In this paper，a design of Glass-on-Silicon interposer with high heat dissipation capacity and excellent RF compatibility was developed. With the manifold micro-channel, large amount of heat can be dissipated directly into the coolant. With the design of a glass layer bonded to the Si substrate, high-frequency device was compatible to the interposer. Low flow resistance was achieved by a special design of double-layer and extremely short micro-channels. The heat dissipation performance of the manifold structure with different channel widths and channel heights was explored by numerical simulation. RF characteristic of the Glass-on-Si interposer was verified by investigating the electrical performance of a coplanar waveguide line (CPW line). The transmission loss was only 20% of the same case for Si interposer.

In this paper, we present an aluminum nitride (AlN) based Piezoelectric Micro-machined Ultrasonic Transducer (PMUT) for contact sensing, which is a suspended stacked layers Si/Mo electrode /AlN/Al electrode in Silicon substrate. In order to obtain a Si elastic layer with a small thickness, DRIE Si process is utilized to make a deep cavity on the backside of Si substrate to suspend the stacked layers of PMUT device. AlN based PMUT sample is fabricated, having a suspended stacked layers of Si/Mo/AlN/Al measured about 5μm/0.1μm /0.8μm/1μm respectively in the thickness, 100μm in the radius of Si film. The AlN film has a measured surface roughness of 5nm by AFM and has (001) orientation peak by XRD analysis.

Narrow bandwidth of miniaturization patch antenna caused by substrate material severely limits its applications, fabricating air cavity on AlN ceramic substrate for decreasing its dielectric constant is a potential method for increasing the bandwidth. But it’s a critical challenge for simultaneous fabricating of surrounding air cavity and TCV holes on AlN ceramic substrate with high precision.This paper presents a patch antenna on AlN ceramic substrate with surrounding air cavity and TCV holes. And its key process of surrounding air cavity and TCV holes fabrication on AlN ceramic is developed by batch-mode μUSM. AlN ceramic simple with step depth of surrounding air cavity and TCV blind hole is machined simultaneously. Its machining feature resolution and surface roughness are below 1μm and Ra 200nm respectively, machining removal rate is higher than 4.5μm/min. The patch antenna property is simulated and analyzed, the results show the increment of bandwidth reach up to 68.42% because of the surrounding air cavity existing.

This paper reports a novel fabrication strategy for flexible electronics based on the parylene-MEMS (micro-electromechanical system) technique. A set of parylene-filled trenches is used to mechanically connect silicon-based functional units and realize a flexible 4$\times$6 temperature controlling array as a preliminary demonstration. The trench-filling performance of the parylene deposition is carefully studied, and an optimized process is established to minimize the keyhole inside the parylene-filled trench. The effect of trench width on the flexibility and bendability of the prepared flexible electronics devices is analyzed by finite element modeling. Performances of the thermal/electrical isolation and the mechanical connection of the prepared parylene-filled trenches have been tested. The experimental results indicate that the highest thermal isolation efficiency is approximately 72.5% with the 10 paralleled, 7 $\mu$m wide and 50 $\mu$m deep parylene-filled trenches. The leakage current of the 10 paralleled, 5 $\mu$m wide and 100 $\mu$m deep parylene-filled trenches is less than 2 pA under a voltage of 100 V. Besides, these parylene-filled trenches acting as the flexible linkage of connected silicon-based functional units exhibit high connection performance without rupture when the loading pressure is under 200 kPa. Due to the powerful silicon microfabrication capability and excellent compatibility of the parylene-MEMS technique, the present flexible electronics strategy holds a promising potential for applications in various areas.

Accurate electrical models for Through Silicon Via (TSV) are critical for 3D integration system design, in which TSV capacitance plays an important role. Minority carrier redistribution (MCR) effect, the spatial position rearrangement of minority carrier in inversion layer, is considered in TSV modeling in this paper. The importance of taking MCR into account is illustrated by comparing the TSV capacitance calculated by capacitance models with and without MCR for a square-shape TSV. Parametric study of errors result from neglecting MCR is performed on several physical and material parameters. A more accurate electrical model for square-shape TSV based on 3D transmission line matrix method (3D-TLM) is proposed, and transient analysis using this model is performed to reveal the effect of MCR on the noise coupling.

In this paper, a TSV interposer embedded with microchannel is proposed for 2.5D integration of GaN RF power device. S-shaped microchannel with symmetrical radial diversion structure in inlet/outlet region is designed to make a balance among process, cooling property and flow resistance. In order to avoid issues regarding to fabrication of TSV interconnections on thick bonded Si wafer embedded with microchannels, TSV is designed as having three different diameters along its axis which are 100mm, 180mm and 220mm in sequence from the bottom end to the top end and total height of 500mm. A process is developed with Si-Si wafer bonding process for the proposed TSV interposer embedded with S-shaped microchannel that is 50mm/100mm in its width/pitch, 300mm in the depth. Sample of TSV interposer embedded with microchannel is fabricated and tested electrically, it has a tested resistance about 6mW for TSV interconnection. In order to validate the proposed TSV interposer, A GaN RF power amplifier chip which has an equivalent thermal flux about 400W/cm2 is utilized as test vehicle and 2.5D integrated GaN RF power amplifier based TSV interposer with embedded cooling microfluidics is designed, assembled and tested. The experimental result show that 2.5D integrated GaN Power amplifier can work correctly.

As Through Silicon Vias (TSV) based System In a Package (SIP) technology is booming, high quality integrated inductor is desired for Radio Frequency (RF) application. Due to the substrate loss, traditional TSV interposer integrated inductor confronts low quality factor (Q) issues. In this study, we present a TSV interposer integrated suspended spiral inductor to address the substrate loss issues. To testify this concept, a process is designed, which is featuring in a releasing process by a combination of Si Deep Reactive Ion Etching (DRIE) and Reactive Ion Etching (RIE) process to achieve TSV interposer integrated suspended inductor. Based on the process, two inductors which are used as test vehicles are designed fabricated and tested. A releasing gap of 40mm is achieved for the samples. One inductor has an inductance of 2nH and a quality factor of 20 at 20GHz, another has an inductance of 5nH and a quality factor of 9 at 5GHz, which are about one times improvement in quality factor and about two times improvement in working bandwidth compared with the referring inductor designs of similar structure but without substrate releasing.

In this paper, TSV interposer integrated 3D high density capacitor is presented, which is featuring in a Metal-Insulation-Metal (MIM) structure on inside surface of blind TSVs array. A process is developed with Al2O3 as insulation layer deposited by Atomic Layer Deposition (ALD). With this process, TSV interposer integrated high density 3D capacitor sample is fabricated, and characterized in terms of capacitance density, leakage current, breakdown voltage, Self-resonant frequency (SRF) and Equivalent series Resistance (ESR). According to the experiment, it has a capacitance density of 5nF/mm2, a leakage current less than 2.5mA at a bias voltage below 10V and a breakdown voltage about 20V, a predicted ESR about W and a ESR about MHz. The reason is investigated with simulation results and optimization direction is assured.

Electronic products used in aerospace environment face severe load condition including mechanical shock, thermal shock and different kinds of radiation. It has been studied for a long time that how radiation influences metal-oxide-semiconductor (MOS) devices but few literatures have been published about that how radiation affects through-silicon via (TSV) -based systems. And therefore we studied the reliability of TSV under the experimental radiation condition of 60Co gamma radiation with a total radiation dose of 500 Gy. Three kinds of samples with different dimensions of TSVs and different processes of oxidation layer were designed and fabricated to measure the leakage current between two adjacent TSVs before and after irradiation. Another kind of sample with an array of TSVs was designed and fabricated to measure the capacitance of TSV parasitic MOS capacitance before and after irradiation. The I-V characteristics showed that the leakage current increased significantly after irradiation and breakdown of silicon oxide of a part of samples layer occurred at a lower voltage after irradiation. The value of the TSV parasitic MOS capacitance decreased obviously and the slope of the C-V characteristic were also changed after irradiation. As a result, it is important and necessary to study the effect of radiation on TSV reliability.

Sapphire has widely used for application to MEMS due to its excellent optical property, mechanical property, chemical stability, high melting point and electrical insulation property, such as X-ray resonator cavities, optical wall shear stress sensor for high temperature applications, lateral overtone bulk acoustic resonator with high f-Q and increasing the output power of LED. This paper presented a high resolution batch-mode micro-utralsonic-machining $(\mu\mathbf{USM})$ with constant feed force of sapphire for MEMS application, and it has advantages of high machining efficiency, resolution and surface quality compared to other machining method. High aspect ratio $(> \mathbf{4})$ structure with the feature resolution below 1μm of sapphire has been machined by batch-mode $\mu\mathbf{USM}$. A machining depth of $\mathbf{40}\mu\mathbf{m}$ has been achieved at a removal rate up-to $\mathbf{4}\mu\mathbf{m}/\mathbf{min}$, and its bottom surface roughness is below Ra 80nm.

The radiation dose dependent sensitivity characteristics of bilateral silicon sensors are studied to improve the radiation hardness under neutron irradiation. Sensors with different effective intrinsic base lengths using 1.5mm ultra-thick silicon substrate are fabricated and the effect of structure parameters on neutron detection sensitivity is experimentally investigated. The simulations of devices with different structures are used to study the influence of potential distribution on radiation hardness characteristics. It is found that, increasing the effective intrinsic base length can improve the sensitivity. The effect of radiation does and working current are investigated experimentally.

In this paper, two versions of capacitive accelerometers based on low-temperature co-fired ceramic (LTCC) technology are developed, different with respect to the detection technique, as well as the mechanical structure. Fabrication of the key structure, a heavy proof mass with thin beams embedded in a large cavity, which is extremely difficult for the conventional LTCC process, is successfully completed by the optimized process. The LC resonant accelerometer, using coupling resonance frequency sensing which is first applied to LTCC accelerometer and may facilitate application in harsh environments, demonstrates a sensitivity of 375 KHz/g over the full scale range 1 g, with nonlinearity less than 6%, and the telemetry distance is 5 mm. The differential capacitive accelerometer adopting differential capacitive sensing presents a larger full scale range 10 g and lower nonlinearity less than 1%, and the sensitivity is 30.27 mV/g.

Along with extensive applications of through-silicon vias (TSVs) in 3-D systems, such as digital, logic, and memory modules, the accurate modeling of coupling capacitance between the TSVs is becoming indispensable to the signal integrity analysis of the system design. In this paper, the static characteristics of potential, electric field, and charges between signal-ground TSVs in a floating substrate are investigated, and accordingly, the effect of MOS capacitance on the coupling capacitance between signal and ground TSVs is accurately modeled and analyzed for both static and high-frequency situations. Furthermore, the impact of substrate admittance on the capacitance-voltage dependence is explored. Parametric studies are performed to study the effects of different physical and material parameters on the coupling capacitance, which include TSV radius, liner thickness, doping concentration, amount of oxide charges, and work function of TSV filling materials. Based on the proposed model, the nonlinear effect of the coupling capacitance on transient noise is examined and explained.

This article presents a simple, non-toxic, and low-cost tips arrays made of poly-dimethylsiloxane pyramidal material, which is expected to have a large-scale application in the future civil biomedical field. A layer of silica and silicon nitride are grown on the silicon wafer as a corrosion mask by thermal oxygen and low pressure chemical vapor deposition process, sequentially. After lithography process, the wafer is wet-etched by potassium hydroxide etchant, and the sharpness of the deep notches can be controlled by controlling the time of corrosion. And then the poly-dimethylsiloxane is poured and filled in a vacuum. By adjusting the vacuum, pouring temperature and time, to achieve poly-dimethylsiloxane defect-free filling. Through the process optimization, to strip the poly-dimethylsiloxane from the deep notches. The quality of the tips are tested and characterized by step meter, optical microscope, as well as scanning electron microscope, and the results show that the stripping effect is very good, and there is no burr on the surface of the poly-dimethylsiloxane pyramidal tips arrays and no other flaws.

A new process flow of fabricating large area thin silicon PIN radiation detectors is presented in this paper. TMAH etching is applied to reduce the thickness of silicon wafers. The thickness of the fabricated detector is 100μm. The diameter of the circular active area is from 0.97mm to 12mm. At reverse bias voltage of 100V, the leakage current of detector with the diameter of 12mm is 5nA. The breakdown voltage of the detectors is over 100V. Analysis indicates that leakage current is mainly induced by surface leakage.

This paper presents one fabrication process of a triple-layer stacked TSV interposer for switch matrix consisting of eight RF chips. There are about 600 TSVs in the interposer and the diameter of TSV is 40um with the aspect ratio being 4:1. The whole area of the interposer is 13.5 mm × 7.5mm and the thickness of the triple-layer stacked interposer is only about 0.7mm. After the process, the electrical properties of RDL and TSV on the interposer are tested and the transmission losses of them are only about 0.2dB and 1.39dB at 4GHz, respectively.

This paper proposes an interposer fabrication methods with annular copper through-silicon via (TSV) and multi-layered redistribution layer. Additives, current density, forced convection and environment temperature are taken into consideration in order to realize the equal-wall annular TSV filling. A multi-layered redistribution layer is fabricated on the front-side of interposer employing electroplating process and photolithographic process. Benzocyclobutene is used as the interlayer dielectric layer. A given number of interposer samples with annular copper TSV and multi-layered redistribution layer are fabricated. X-ray inspection and cross section observation are carried out to support the good quality of this proposed interposer integration approach.