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As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Interposers will be needed more complicated structure for 2.5D , 3D package and MEMS, OEMEMS new heterogeneous package structure Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. [1] This paper presents the demonstration of Silicon Interposers with fine pitch through Silicon vias(TSV),with embedded passive device. We have developed the TSV interposer with redistribution layers on both sides using MEMS technology, high aspect ratio deep etching technology and filled Cu plating with deep through holes for cost reduction and low electrical loss. The TSV interposer with 400μm thick high resistivity Si, obtained without backside processing use of carriers. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TSV at 200μm pitch passed 1000 thermal cycles from −55°C to 125°C. We have evaluated high frequency transmission characteristic of Si through hole by the measurement S21 parameter. Highly insulating TSV resulted in insertion loss of less than 1dB at 20GHz. Thin film SiN capacitor as embedded passive device was built in surface of TSV interposer by via first and via last method. The capacitance and leakage current of capacitor was measured and compared with two types of fabrication method.

As electronic product becomes smaller and lighter with an increasing number of function ↚ the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of TSV interposers and TGV interposers with fine pitch high aspect ratio through vias.

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of glass interposers with fine pitch metalized through via. The application of glass interposer to 2.5D integration of multiple chips requires ultra-fine line and space. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating used for RDL. High frequency transmission characteristics were measured with TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Glass interposer with conformal plated via demonstrated on 300mm panel format. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000 cycle from −40 cereuses deg to 80 cereuses deg.

As electronic product becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50µm diameter) are fabricated today with 300µm thick glass. This paper presents the demonstration of glass interposers with fine pitch metalized through via. The application of glass interposer to 2.5D integration of multiple chips requires ultra-fine line and space. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating used for RDL. High frequency transmission characteristics were measured with TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Glass interposer with conformal plated via demonstrated on 300mm panel format. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000cycle from −40 cereuses deg to 80 cereuses deg.

As electronic products becomes smaller and lighter with an increasing number of function, the demand for high density and high integration becomes stronger. Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several years. Fully populated wafers with >100,000 through holes (50μm diameter) are fabricated today with 300μm thick glass. This paper presents the demonstration of silicon and glass interposers with fine pitch metalized through via. High frequency transmission characteristics were measured with TSV and TGV co planer wave guide. Twin types of Cu plating method with through via, full filling plating and conformal plating are compared with process capability using X ray observation. Electrical characteristics are measured with daisy chain test elementary vehicle. Excellent through via reliability was demonstrated at 200um pitch passed 1000 cycle from −40 Celsius deg to 80 Celsius deg.

As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger.! Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration;! however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several months. Fully populated wafers with > 100,000 through holes (50μm diameter) are fabricated today with 300pm thick glass. This paper presents the demonstration of glass interposers with fine pitch through glass vias(TGV), ! with 6um RDL lithography. TGVs of 50μm in diameter and 200μm in pitch were formed successfully on 300μm thick alkali-free glass by Focused Electrical Discharging Method (FEDM). The TGVs were filled with solid Copper (Cu) using a void-free electroplating of optimized periodic pulse reverse(PPR) process and chemical mechanical polishing (CMP) as well as the TSVs. Highly insulating TGV with double side polymer insulation resulted in TGV with an insertion loss of less than 0.23dB at 20GHz. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TGV at 200μm pitch passed 1000 thermal cycles from -40Cdeg to 85Cdeg.

To hermetically seal a hybrid IC with several EPROM IC ships, sapphire windows are brazed to a metal cap. Since it was necessary to investigate the pressure resistance of the sapphire windows, stress analysis was performed using the finite element method. In stress analysis, we consider the thermal stress generated in brazing the sapphire window on the metal cap, the forced stress generated in the hermetic seal process of the hybrid IC and the pressured stress generated in the hybrid IC. The allowable stress in sapphire was measured by the bending test with two-point support to obtain the stress limit of sapphire. The theoretical and experimental results were compared to confirm the validity of the analytical model. The analytical method developed in this study will be helpful to achieve high reliability in a hybrid IC with sapphire windows.