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As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating voltage is now limited by Vx to Mx spacing. This spacing has historically been a challenge since the introduction of self-aligned vias due to the loss of CD and chamfer control in the non-self-aligned direction. As pitch continued to shrink from self-aligned via introduction around the 22 nm node, the fraction of via CD control and edge placement compared to the dielectric spacing between interconnects has continued to grow. Alone this trend could be combated by increasing the dielectric spacing, however, the exponential increase in Cu resistivity (under scaling) has forced BEOL technologies into strong line/space asymmetry to keep line resistance under control. At pitches below 32 nm these factors reach a tipping point, either design to exponentially increasing line resistance or lower the technology Vmax. Both approaches cause performance degradation to achieve pitch scaling

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

The metallization of integrated circuits for high performance CMOS devices involves the use of copper with low-k or ultra low-k dielectrics to reduce RC delay and cross talk in devices. For the 90nm to 14 nm CMOS device nodes, conventional silicon nitride was replaced by new dielectric barrier low k materials such as SiCN, C-Rich SiCN and SiNO (1-6). As devices scale down to x film deposited by plasma enhanced CVD with TMS+NH3 is still robust down to around 15-20 nm thickness range. This paper presents the development of the second generation robust Low Hydrogen SiCN to enable cap thickness reduction to EXPERIMENT The low hydrogen SiCNx films were deposited in a commercial high throughput production worthy 13.6 MHz RF 300 mm Plasma Chemical Vapor Deposition process (PECVD) system at 350 C using a combination of Trimethyl Silane (TMS) + Ammonia (NH3) + Hydrogen precursors with excellent uniformity (1 sigma < 1 %). The as-deposited films were analyzed using various electrical , mechanical and chemical analyses to study the film's properties and compositions, Table 1. An oxidation resistance test (6) was done after the barrier film/copper blanket stack was annealed at 310°C for 24 hours in ambient atmosphere. Multi-level 7nm copper interconnect structures were built for Electro-migration (EM) and Time Dependent Dielectric Breakdown (TDDB) reliability measurement (150-300°C). RESULTS and DISCUSSION Table 1 summarizes SiCN and Low H SiCN cap film properties and device performance. Overall, the low H SiCN cap has better electrical, mechanical, and device reliability performance than the standard SiCN cap. The low H SiCN film has higher density, modulus, hardness and significantly higher compressive stress, both as-deposited and post 5 minutes direct UV cure. Compositional analysis shows that PECVD SiCNx cap films deposited with the addition of hydrogen precursor actually have less hydrogen than films deposited without hydrogen under the same optimized deposition condition. Film deposition rates decrease slightly at higher hydrogen flow rate in the TMS+NH3+H2 precursor chemistry. The reduced deposition rate and the hydrogen reduction in the film’s bulk are attributed to the increase removal (etching) of weakly bonded -Si-Hx and -N-Hy species in the film during the plasma deposition process. FTIR analysis shows that Si-C and Si-N bonding density increases in the low H SiCN dielectric, which is consistent with the increase in film density, modulus and harness. A minor reduction in the dielectric constant, similar breakdown voltage and reduced leakage are observed for the low H SiCN cap. Figure 1 shows a typical Scanning Transmission Electron Micrograph (STEM) of a 3nm Co/10 nm Low H SiCN cap on a Copper Metal2 7nm interconnect structure. This Cu/Co/Low H SiCNxcap structure achieves 4-10X better EM/TDDB reliability versus a similar structure with the standardcap (Table 1). A Scanning Electron Micrograph (SEM) of the patterned surface after annealing at 310°C for 24 hours in ambient atmosphere (Figure 1) shows that the 10 nm Low H SiCN cap has excellent Cu Oxidation properties with no sign of Cu Oxidation. CONCLUSIONS Low hydrogen SiCN dielectrics with improved mechanical, oxidation and Cu diffusion barrier properties versus standard SiCN were deposited using TMS, NH3 and H2. The new robust low hydrogen SiCN dielectric cap film showed a significant increase in Si-C and Si-N bonding density and a reliability performance improvement in 7 nm Cu interconnect structures at Acknowledgment This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities. The author would like to thank B. Peethala for some analysis and A. Grill for discussion. REFERENCES [1] L. Xia, M. Naik, H. Xu, V. Zubkov, R. Bhatia, C. Peterson, M. Spuller, and H. M’Saad, Proceeding of Advanced Metallization for Devices and Circuits, (2006) pp. 169. [2] S.G. Lee et al, Jpn. J. Appl. Phys., 40, 2663 (2001). [3] Al Grill, Steve Gate, Son Nguyen, D. Priyadarshin, E Tood Ryan; Appl. Phys. Rev. 1, 011306 (2014). [4] Son V. Nguyen et al., Electrochem. Soc. Transaction 2014, Volume 61, issue 3, pp.17-28. [5] C.Yang et al., IEEE Electron Device Letter, Vol 33, No, 4, pp.588-560 (2012). [6] Son Nguyen et al., Electrochem. Soc. Transaction. 2010, Volume: 33, Issue: 12, pp.137-145. Figure 1

Ever since Al(Cu) wires were replaced by Cu to reduce RC delay, the development of lower k dielectric materials has been a challenge to the back end of line (BEOL) process [1,2]. Copper wiring with low-k or ultra low-k (ULK) dielectrics for high-performance CMOS IC’s requires the use of a robust dielectric cap barrier to prevent inter- and intra-level Cu diffusion and also to maintain device yield and reliability. Plasma Enhanced Chemical Vapor Deposited (PECVD) low-k SiCNH and SiN are the predominant dielectric Cu diffusion caps used by the industry, in part due to the strong cap/Cu debond energies [3]. This paper will present the ultrathin ( We developed a new cyclic multilayer conformal ultrathin (8-14 nm) SiN deposition process to improve Cu CMP recess step coverage. This process includes cyclic low rf power plasma deposition of nano thick (~2 nm) SiN using Silane and Ammonia gases and then subsequent variable rf plasma power Nitrogen (N2) plasma treatment to minimize Cu sputtering and diffusion. The process is repeated in a cyclical manner until desirable film’s thickness is achieved, figure 1. The film deposition step and it enhanced STEM and EDX step coverage images for the post-CMP top corner Cu recess divot structure as showed in figure 2. The Triangular Voltage Test (TVS) and oxidation barrier (310 C, 24 hr exposure in air) evaluation showed this thin (10-14 nm thick ) SiN cap is a good oxidation and Cu barrier. Optimal cyclic SiN film has higher breakdown voltage and lower low leakage than standard SiCNH cap, even after exposure to UV cure, figure 3. As deposited, the SiN film has compressive stress in 500 MPa range. After UV direct UV exposure for 180 sec at 380C, the film’s stress still retain at 300 Mpa compressive. The cyclic SiN cap has excellent modulus of 159 GPa and hardness of 24 GPa. BEOL 80 nm pitch device electrical data showed that device reliability of the 10-12 nm SiN cap film are about comparable to standard 25 nm SiCNH cap but with significant lower device capacitance. SUMMARY A new generations of ultra-thin ( Acknowledgments: This work was performed by Alliance Teams at various IBM Research and Development Facilities and at University at Albany Nanotech Foundation. References [1]Y. Ushiki et al., Proceeding of the VLSI Multilevel Interconnection, (1990) pp. 413 [2] S. P. Jeng et al., Proceeding of Advanced Metallization for Devices and Circuits, (1994) pp. 25. [3] J. R. Lloyd et al., IEEE Transaction on Devices and Materials Reliability, vol. 5, no.1, pp.113-118, March 2005.

Robust ultrathin (20 nm) trilayer low k SiNx/SiNy/SiCNH dielectric Cu caps (k ~4.0-4.2) with post ultraviolet (UV) cure compressive stress were developed and integrated into 22nm CMOS Back End Of Line (BEOL) devices. The new cap reduces device's capacitance (~ 4 %) and enhances stress stability in Cu-Ultra low k structures