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SmTiO3/SrTiO3 interfaces are of potential interest for electronic devices as they exhibit novel electronic phenomena such as metal–insulator transitions. However, good transistor performance from t...

The design and modeling of dielectric superjunction transistors using combinations of ultrahigh permittivity materials and high-mobility materials are described. We show that placing high dielectric permittivity materials in the gate–drain depletion region can reduce electric field variations by screening the field due to depleted charges. This enables simultaneously high sheet charge density and breakdown voltage for scaled field-effect transistors. Using detailed 2-D device simulation of dc and high frequency characteristics, we show that extreme dielectric constant engineering provides unique opportunities for transistor design and has the potential to perform better than state-of-the-art millimeter-wave and terahertz frequency transistors.

High harmonic generation in solids attracted great attentions as a new scheme for frequency conversion. We report observation of an extremely efficient terahertz (THz) third- and fifth-harmonic generation in thin films of Cd3As2, a three-dimensional Dirac semimetal with massless electron dispersion, as it is observable with tabletop THz source at room temperature. Our THz pump-THz probe study with subcycle time resolution elucidates that the intraband current of coherently accelerated Dirac electrons is the main source of the THz harmonics as expected theoretically. The results pave the way toward novel devices for ultrafast THz electronics and photonics based on topological semimetals.

Doped SrTiO3 thin films are of significant scientific interest for their superconducting, ferroelectric, and thermoelectric properties. Air-exposed thin films of doped SrTiO3 suffer from surface carrier depletion that makes it difficult to obtain thin, conducting films, especially at low doping densities and temperatures. Here, we show that thin (10 nm) EuTiO3 capping layers can prevent surface depletion and allow for conducting heterostructures with SrTiO3 films as thin as 10 nm. We also investigate the superconducting properties of EuTiO3 capped SrTiO3 films. We show that the superconducting transition temperature decreases systematically as the SrTiO3 film thickness is reduced, which is likely due to proximity effects.

(001)-oriented thin films of the three-dimensional Dirac semimetal cadmium arsenide can realize a quantum spin Hall insulator and other kinds of topological physics, all within the flexible architecture of epitaxial heterostructures. Here, we report a method for growing (001) cadmium arsenide films using molecular beam epitaxy. The introduction of a thin indium arsenide wetting layer improves surface morphology and structural characteristics, as measured by x-ray diffraction and reflectivity, atomic force microscopy, and scanning transmission electron microscopy. The electron mobility of 50-nm-thick films is found to be 9300 cm2/Vs at 2 K, comparable to the highest-quality films grown in the conventional (112) orientation. This work demonstrates a simple experimental framework for exploring topological phases that are predicted to exist in proximity to the three-dimensional Dirac semimetal phase.

We report an electron transport study of an La-doped perovskite oxide BaSnO3 thin film grown by molecular beam epitaxy on (110) DyScO3 as a function of electron concentration, by etching the film step-by-step with nanometer precision. Inductively coupled plasma-reactive ion etching with BCl3/Ar plasma is used for etching depth control. The local doping and electron density are experimentally determined after each etching step. The results show that the electron mobility is dominated by threading dislocations if the electron concentration is below 7.8 × 1019 cm−3, while ionized impurities and phonon scattering become more dominant at electron concentrations greater than 1.2 × 1020 cm−3. The charging state of thread dislocations is estimated to be 6.2. Furthermore, using the etch process to control the electron concentration and channel thickness, a gate-recessed ferroelectric field effect transistor is fabricated with 10 nm HfO2 as a gate dielectric. The device exhibits a saturation current of 29.9 mA/mm with a current on/off ratio of Ion/Ioff = 8.3 × 108 and a ferroelectric polarization charge density of 1.9 × 1013 cm−2. Under the forward gate bias sweep, the device operates in the enhancement mode with a threshold voltage of 3 V. Under the reverse gate sweeping bias, the device operates in the depletion mode with a threshold voltage of –1.5 V.

This paper describes the fabrication and measurement of tunable, lumped-element parallel-plate capacitors (PPC). The devices utilize electric-field tunable Ba x Sr (1-x) TiO 3 (BST) thin films grown by hybrid molecular beam epitaxy (MBE) on SrTiO 3 (STO) substrates. A high-quality interface was achieved by hot-sputtering epitaxial Pt top electrodes after an in-situ anneal in O 2 . The Pt top electrode and the BST mesa were etched by two separate ion milling steps while the Pt metallization was thickened with Ti/Au to facilitate probing. The fabricated devices consisted of one-port PPCs which were directly probed by ground-signal-ground (GSG) RF probes. The devices were biased using a bias tee on the measurement port while wideband RF scattering parameters were measured from 100 MHz to 10 GHz. The PPCs exhibit a high quality factor of 720 at 100 MHz which drops to 120 at 1 GHz due to the large device area and parasitic electrode resistance. This parasitic resistance was exacerbated by measuring with relatively wide-pitch probes. The high quality factor combined with 2.2:1 tunability yields an exceptionally high commutation quality factor CQF of 750,000 at 100 MHz, 2000 at 1 GHz, and 200 at 10 GHz. These results are the first RF results of MBE-grown PPCs and demonstrate the extremely high quality of BST grown by hybrid MBE.

The etching of epitaxially grown perovskite oxide BaSnO3 (BSO) and BaTiO3 (BTO) thin films is studied using Cl-based (BCl3/Ar) and F-based (CF4/Ar) plasma chemistries in an inductively coupled plasma reactive ion etching (ICP-RIE) system for the development of field effect transistors (FETs). It is found that the BCl3/Ar process has a time-independent and a higher etch rate and creates a smooth etched surface, while the etch rate of BSO and BTO in CF4/Ar plasma decreases with the etching time duration. For the BCl3/Ar etching process, the etch rate increases with both ion density and ion energy, suggesting the combination of chemical plasma etching and physical ion sputtering mechanisms. Using the Cl-based etching process, BaSnO3 and BaTiO3 heterojunction FETs are developed. The devices with a gate length of 1.5 μm have a saturation current density of 287.6 mA/mm, a maximum transconductance of gm = 91.3 mS/mm, an FET mobility of 45.3 cm2/V s, and a threshold voltage of −1.75 V. The etching processes developed in this work will enable further development of perovskite oxide heterostructure electronic devices.The etching of epitaxially grown perovskite oxide BaSnO3 (BSO) and BaTiO3 (BTO) thin films is studied using Cl-based (BCl3/Ar) and F-based (CF4/Ar) plasma chemistries in an inductively coupled plasma reactive ion etching (ICP-RIE) system for the development of field effect transistors (FETs). It is found that the BCl3/Ar process has a time-independent and a higher etch rate and creates a smooth etched surface, while the etch rate of BSO and BTO in CF4/Ar plasma decreases with the etching time duration. For the BCl3/Ar etching process, the etch rate increases with both ion density and ion energy, suggesting the combination of chemical plasma etching and physical ion sputtering mechanisms. Using the Cl-based etching process, BaSnO3 and BaTiO3 heterojunction FETs are developed. The devices with a gate length of 1.5 μm have a saturation current density of 287.6 mA/mm, a maximum transcond...

We report on in-situ surface preparation methods prior to atomic layer deposition (ALD) of gate dielectrics on In0.53Ga0.47As, and investigate their influence on the ability to scale the equivalent oxide thickness (EOT) and to reduce interface trap densities (Dit ). The surface treatments employed here consist of in-situ cleaning involving alternating cycles of nitrogen plasma and trimethylaluminum (TMA) pulses prior to ALD of different dielectrics (1,2). We demonstrate metal-oxide-semiconductor capacitors with HfO2 dielectrics and low Dit (in the mid 1012 cm-2 eV-1 range) that can be scaled to sub-nm EOT. Accumulation capacitances exceed 3 µF/cm2 at 1 MHz on n-type In0.53Ga0.47As. Complementary studies of interface chemistry and surface morphology using transmission electron microscopy, x-ray photoelectron spectroscopy, and secondary ion mass spectrometry as a function of surface cleaning parameters are presented and elucidate the mechanisms by which these novel surface preparation methods allow for reducing both Dit and EOT.

Cadmium arsenide (Cd3As2) is a three-dimensional Dirac semimetal with many unique electronic properties that are of interest for future device applications. Here, we demonstrate field effect transistors using Cd3As2 as the channel material. We show that current densities exceed 5 A/mm and that very low contact resistances can be achieved even in unoptimized device structures. These properties make Cd3As2 of great interest for future high-speed electronics. We report on the current modulation characteristics of field effect transistors as a function of temperature. At low temperatures, the modulation exceeds 70%. We discuss material and device engineering approaches that can improve the device performance at room temperature.

Point defects are unavoidable, and they can substantially modulate a material's electronic, magnetic, and structural properties. Quantitative scanning transmission electron microscopy is used to reveal strontium vacancies in SrTiO${}_{3}$ films.

This paper describes the fabrication, measurement, and modelling of radio-frequency (RF), tunable interdigital capacitors (IDC). The devices utilize electric-field tunable BaxSr(1−x)TiO3 (BST) thin films grown by hybrid molecular beam epitaxy (MBE) on LaAlO3 (LAO) substrates, a first growth of its kind. A high-quality interface was achieved by hot-sputtering epitaxial platinum. S/L-band IDCs demonstrate high quality factors (200) combined with 47% tunability. The devices demonstrate a commutation quality factor averaging 6,000 across the L band. A phase shifter unit cell was simulated and implemented using the IDC equivalent circuit parameters.

We report raised source/drain (S/D) InAs quantum well MOSFETs incorporating a vertical spacer formed by metal–organic chemical vapor deposition epitaxial regrowth. By adopting a 12-nm-thick vertical spacer between the channel and the ${\rm N}+{\rm S}/{\rm D}$ , off-state characteristics are significantly improved. A device with a 40-nm- $L_{g}$ and 12-nm-thick spacer shows 2.5- ${\rm mS}/\mu{\rm m}$ peak transconductance $(g_{m})$ , 86-mV/decade subthreshold swing at $V_{DS}=0.5~{\rm V}$ , 83-mV/V drain-induced barrier lowering, and 482- $\mu{\rm A}/\mu{\rm m}$ ON-current at 100- ${\rm nA}/\mu{\rm m}$ OFF-current and $V_{DD}=0.5~{\rm V}$ . In addition, a 3.0- ${\rm mS}/\mu{\rm m}$ peak $g_{m}$ at $V_{DS}=0.5~{\rm V}$ is achieved in an 18-nm- $L_{g}$ device with a 2-nm-thick spacer, the highest reported peak $g_{m}$ of any field-effect transistor.

The low solubility of Er in GaAs results in the formation of ErAs nanostructures when GaAs is grown with 5–6 at% Er/Ga ratio by molecular beam epitaxy on GaAs surfaces. For growth on the (4 1 1)A GaAs surface, cross-sectional scanning transmission electron microscopy images show the presence of ErAs nanorods embedded in a GaAs matrix extending along the [2 1 1] direction with a spacing of roughly 7 nm and a diameter of roughly 2 nm. Growth on the GaAs (4 1 1)B surface resulted in only nanoparticle formation. Variation of the polarized optical absorption with in-plane polarization angle is consistent with coupling to surface plasmon resonances of the semimetallic nanostructures.

We describe the molecular-beam epitaxial (MBE) growth and fabrication of III–V metal-oxide-semiconductor (MOS) devices on Ge/Si virtual substrates. We show that high-temperature in-situ H2 annealing in the chemical-vapor deposition system changes the Ge surface configuration and produces a surface with predominantly double-step-layer conditions, which is crucial for the growth of single-domain GaAs. In addition, the surface morphology of III–V on Ge/Si improved significantly with an annealing treatment of the Ge surface carried out under high arsenic background pressure in the MBE chamber. This facilitates uniform As-monolayer formation on the entire Ge surface. Low-temperature migration-enhanced epitaxy (MEE) and low-temperature conventional GaAs growth not only enhance the growth of single-domain GaAs without Ge outdiffusion but also produce a sufficiently smooth surface for high-k dielectric deposition, achieving low leakage current. A 300-nm-thick GaAs buffer layer was grown, followed by a 10 nm growth of In0.2Ga0.8As high-mobility channel layer. A 7–8-nm-thick Al2O3 layer was deposited ex-situ by atomic-layer deposition (ALD). We verify the quality of III–V growth using transmission electron microscopy (TEM), X-ray diffraction (XRD), secondary ion mass spectrometry (SIMS) and photoluminescence (PL) measurement. The C–V characteristics show unpinning of the Fermi level, which is a necessary condition for gate voltage control of the drain current. This work suggests this materials combination is a promising candidate for the realization of advanced, nonclassical complementary-MOS and optoelectronic devices on Si substrates.

Advanced gate dielectric stacks are comprised of multiple layers of different materials, including high-k gate dielectrics, metal gate electrodes and interfacial layers with sub-nanometer thickness. The composition, point defect chemistry, interface atomic structure and interaction between the layers determine the properties of these gate stacks. This paper reviews recent applications of advanced scanning transmission electron microscopy techniques to determine the atomic structure and defects in advanced gate stacks.

We present reliability analysis of the two most critical interfaces in III-V Heterojunction Tunnel FET (HTFET) design: (1) Tunnel Heterojunction is characterized in three-dimensional atomic scale resolution using Atom Probe Tomography. We explore the impact of tunnel junction abruptness and source dopant fluctuations on HTFET performance; (2) Extremely scaled Hi-K gate dielectric (sub-0.8 nm EOT: HfO2, HfO2-ZrO2 bilayer, and ZrO2)/ III-V channel interface is evaluated using Positive Bias Temperature Instability (PBTI) measurements. HfO2 based HTFET exhibits superior PBTI performance over ZrO2 based HTFET and shows lifetime improvement over III-V FinFET.

Resistive switching effects in transition metal oxide-based devices offer new opportunities for information storage and computing technologies. Although it is known that resistive switching is a defect-driven phenomenon, the precise mechanisms are still poorly understood owing to the difficulty of systematically controlling specific point defects. As a result, obtaining reliable and reproducible devices remains a major challenge for this technology. Here, we demonstrate control of resistive switching based on intentional manipulation of native point defects. Oxide molecular beam epitaxy is used to systematically investigate the effect of Ti/Sr stoichiometry on resistive switching in high-quality Pt/SrTiO3 junctions. We demonstrate resistive switching with improved state retention through the introduction of Ti- and Sr-excess into the near-interface region. More broadly, the results demonstrate the utility of high quality metal/oxide interfaces and explicit control over structural defects to improve control, uniformity and reproducibility of resistive switching processes. Unintentional interfacial contamination layers, which are present if Schottky contacts are processed at low temperature, can easily dominate the resistive switching characteristics and complicate the interpretation if nonstoichiometry is also present.

Extremely scaled high-k gate dielectrics with high quality electrical interfaces with arsenide (As) and antimonide (Sb) channels are used to demonstrate complimentary ‘all III–V’ Heterojunction Vertical Tunnel FET (HVTFET) with record performance at |V DS |=0.5V. The p-type TFET (PTFET) has I ON =30µA/µm and I ON /I OFF =105, whereas the n-type TFET (NTFET) has I ON =275µA/µm and I ON /I OFF =3×105, respectively. NTFET shows 55mV/decade switching slope (SS) while PTFET shows 115mV/decade SS in pulsed mode measurement. Vertical TFET offers 77% higher effective drive strength than Si-FinFET for given inverter standard cell area. Energy-delay performance of TFET shows gain over CMOS for low V DD logic applications.

Planar ultrathin InAs-channel MOSFETs were demonstrated on Si substrates with gate lengths (L g ) as small as 20 nm. The III-V epitaxial buffer layers were grown on 300 mm Si substrates by metal-organic chemical vapor deposition (MOCVD) and the subsequent InAlAs bottom barriers and InAs channel were grown by molecular beam epitaxy (MBE). The devices at 20 nm L g show high transconductance, ∼2.0 mS/μm at V DS =0.5V.

Strontium hafnate films are predicted to have desirable properties for use as a high-permittivity gate insulator. Such a film is of extreme interest to the scaling of Metal Oxide Semiconductor (MOS) transistors. Thin films of strontium hafnate have been prepared by cosputtering of Hf and SrO2. Strontium rich films appear to resist crystallization up to temperatures of 1000 °C, although high resolution electron microscopy suggests that nanocrystals form after high temperature annealing. Early measurements of MOS capacitors indicate a permittivity of approximately 35 and a lowest bandgap of about 4.4 eV.

In integrated circuit designs, smaller is better; high permittivity films allow circuit designers to save substrate space, but the small geometries of such devices introduce parasitic effects. In this work we investigate the relationship between device geometry and capacitance density, quality factor, and leakage current density. The devices in this study have electrode areas ranging from 12 × 12 μm2 to 45 × 45 μm2. For each electrode area we have structures with 5 μm, 7.5 μm, 10 μm, 12.5 μm and 15 μm mesa ledges.

Bismuth zinc niobate (BZN), a high dielectric constant material that combines low dielectric losses with an electric-field dependent permittivity, was implemented as the dielectric in metal-insulator-metal (MIM) capacitors. Dielectric properties up to 20 GHz were evaluated by measuring reflection coefficients with a vector network analyzer. The dielectric constant was around 180 and the quality factor remained greater than 100 up to 5 GHz for 64 μ m2 devices. No onset of dielectric relaxation, as seen in bulk ceramic data, could be detected in the measured frequency range. The results show that BZN thin films have great potential for low loss, tunable microwave devices.

The microstructure and orientation relationships of epitaxial (111)-oriented SrTiO3 thin films grown by radio frequency magnetron sputtering on epitaxial (111)-oriented Pt/Ti electrodes on sapphire were investigated using x-ray diffraction, conventional and scanning transmission electron microscopy. We show that the epitaxial growth of (111)-oriented SrTiO3 films was promoted by thin Ti adhesion layers underneath the Pt electrode. The SrTiO3 films nucleated with two twin-related orientation variants, rotated by 180° about the 〈111〉 surface normal. The twin boundaries were oriented approximately normal to the film plane, but no strong preference for a specific boundary plane was observed. Growth mechanisms and the relationships to the dielectric properties are discussed.

High-k metal oxide gate dielectrics may be required to extend Moore’s law of semiconductor device density scaling into the future. However, growth of a thin SiO2-containing interface layer is almost unavoidable during the deposition of metal oxide films onto Si substrates. This limits the scaling benefits of incorporating high-k dielectrics in future transistors. A promising approach, in which oxygen-gettering metal overlayers are used to engineer the thickness of the SiO2-based interface layer between metal oxide and Si substrate after deposition of the metal oxide layer, is reported. Using a Ti overlayer with high solubility for oxygen on ZrO2 or HfO2 dielectrics, the effective removal of the low-k interface layer at 300K has been confirmed by electron microscopy and spectroscopy techniques. Significant enhancement of the gate capacitance density, while retaining low leakage current densities, has also been demonstrated for these interface-engineered high-k gate stacks.

For this paper, we used radio-frequency (rf) sputter deposition to synthesize epitaxial La0.5Sr0.5CoO3−∂ (LSCO) films. We investigated the influence of sputter deposition parameters, in particular, oxygen partial pressure, plasma power, total sputter pressure, and post-deposition cooling atmosphere on film composition, microstructure, and electrical resistivity. We show that rf sputtering from a single target can produce LSCO films with La/Sr and (La + Sr)/Co ratios of unity and with low electrical resistivities of about 1 mΩ cm. Film microstructures were characterized by high-resolution transmission electron microscopy and x-ray diffraction. Formation of an ordered film superlattice, most likely due to oxygen vacancy ordering, was observed. In this paper, we discuss the relationship between the film microstructure and the electrical resistivity.

We report enhancement-mode composite-channel (In0.53Ga0.47As/InAs/In0.53Ga0.47As) MOSFETs fabricated using a substitutional-gate process, with n+ relaxed InAs source-drain regions formed by regrowth by molecular beam epitaxy. A device with 70-nm gate length and 2-nm In0.53Ga0.47As/3.5-nm InAs/3-nm In0.53Ga0.47As channel showed a peak transconductance of greater than 0.76 mS/μm at Vds = 0.4 V and showed Id = 0.5 mA/μm at Vds = 0.4 V and Vgs - Vth = 0.7 V. The subthreshold swing at Vds = 0.1 V was 130 mV/dec.

We report on the growth of epitaxial Sr2RuO4 films using a hybrid molecular beam epitaxy approach in which a volatile precursor containing RuO4 is used to supply ruthenium and oxygen. The use of the precursor overcomes a number of issues encountered in traditional MBE that uses elemental metal sources. Phase-pure, epitaxial thin films of Sr2RuO4 are obtained. At high substrate temperatures, growth proceeds in a layer-by-layer mode with intensity oscillations observed in reflection high-energy electron diffraction. Films are of high structural quality, as documented by x-ray diffraction, atomic force microscopy, and transmission electron microscopy. The method should be suitable for the growth of other complex oxides containing ruthenium, opening up opportunities to investigate thin films that host rich exotic ground states., In press, APL Mater

Integration of ultrathin ferroelectric thin films with semiconductors is of interest for negative capacitance transistors that exhibit internal voltage gain, which may allow for scaling the supply voltage of low power circuits. In this study, BaTiO3 thin films were grown on doped SrTiO3 channels using molecular beam epitaxy. The BaTiO3 films are ferroelectric despite their low thickness (∼10 nm). Parallel plate capacitor devices exhibit anti-clockwise hysteresis, and a comparison with reference structures without BaTiO3 shows that the polarization in the BaTiO3 thin films is switchable and controls the charge density in the channel. Field effect transistors were fabricated to study the effect of ferroelectricity on the transistor characteristics. Anti-clockwise hysteresis and a shift in threshold-voltage are observed in the output characteristics of the transistors. These properties make these heterostructures a suitable system for studying negative capacitance effects.

We report InGaAs-channel MOSFETs using recessed InP spacer layers in the regrown source and drain. By replacing narrow band-gap InGaAs with wide band-gap InP within the high-field region near the drain end of the channel, band-to-band tunneling (BTBT) leakage is significantly reduced. A 30 nm gate length device using InP spacers shows a minimum I off ∼60 pA/µm, approximately 100∶1 smaller than a similar device using InGaAs source/drain spacers. A FET using InP spacers, with 45 nm gate length, and with a 3 nm ZrO 2 gate oxide shows I on =150 µA/µm at I off =1 nA/µm and V DS =0.5 V. The low off-state leakage current observed with InP source/drain spacers makes InGaAs MOS technology viable for low-power logic.

We report the fabrication of low-leakage rectifying Pt and Au Schottky diodes and Au-gated metal-semiconductor field effect transistors (MESFETs) on n-type SrTiO3 thin films grown by hybrid molecular beam epitaxy. In agreement with previous studies, we find that compared to Pt, Au provides a higher Schottky barrier height with SrTiO3. As a result of the large dielectric constant of SrTiO3 and the large Schottky barrier height of Au, the Au-gated MESFETs are able to modulate ~1.6 x 1014 cm-2 electron density, the highest modulation yet achieved using metal gates in any material system. These MESFETs modulate current densities up to ~68 mA/mm, ~20x times larger than the best demonstrated SrTiO3 MESFETs. We also discuss the roles of the interfacial layer, and the field-dependent dielectric constant of SrTiO3 in increasing the pinch off voltage of the MESFET., Accepted for publication in Applied Physics Letters

Because InGaAs has a small bandgap, InGaAs MOSFETs are vulnerable to large band-to-band tunneling currents, arising near the drain end of the channel. This sets a minimum off-state leakage current, and can render the device unsuitable for VLSI applications at sub-10-nm gate lengths. Here we report two techniques to reduce band-to-band tunneling leakage in InGaAs MOSFETs. By using either a recessed InP wide bandgap spacer in the regrown source/drain region or, alternatively, an InP channel cap on top of InGaAs channel, off-state leakage can be reduced to 1 nA/μm for 22 nm gate length devices. These two techniques pave the way for application of III-V InGaAs MOSFETs in low power logic.

We report MOSFETs with 25-nm gate length (L g ), extremely thin 2.5 nm InAs channels and 0.7/3.0 nm (physical) Al 2 O x N y /ZrO 2 gate dielectrics, and 12 nm In 0.53 Ga 0.47 As vertical spacers in the raised epitaxial source/drain. The FETs establish key new DC performance records, at VLSI-relevant gate lengths (25 nm), including 0.50 mA/μm on-current (at 100 nA/μm I off and 0.5 V V DD ) and 77 mV/dec. subthreshold swing (SS) at V DS =0.5 V. At 1 μm L g and V DS =0.1 V, the minimum subthreshold swing is 61 mV/dec., a record low for InAs/InGaAs, indicating high interface quality.

The polar discontinuity [1] and electronic reconstruction at the interface of SrTiO3 and GdTiO3 leads to a unique high two dimensional electron gas (2DEG) of 3×10 14 electron/cm 2[2] , that is exactly half of the number of unit cells at the interface. The ability to modulate this high charge density could enable a new class of oxide electronics and plasmonics devices that harness extreme charge density. In this work show how heterostructures field effect transistors can be designed to enable modulation of over 10 14 cm -2 electron/cm 2 , where represents the highest charge density modulated in any field effector transistor to date.

Recently, InAs or In-rich InGaAs (In>53%) has been widely studied as the channel material for III-V FETs due to its superior electron transport properties over In 0.53 Ga 0.47 As. These materials provide excellent on-state characteristics, e.g. >2.5 mS/μm peak transconductanc (g m ) at V DS =0.5 V [1-3]. The narrow bandgap in these materials, however, causes band-to-band tunneling (BTBT) in the high drain-field region even at relatively low supply voltage of 0.5 V, thus resulting in high leakage at the off-state [1][3]. In our previous work, in order to address this issue, we incorporated a vertical spacer between the channel and N+ source/drain (S/D) to accommodate the depletion region near the channel-drain junction. The spacer significantly improved off-state characteristics such as off-state leakage, drain-induced barrier lowering (DIBL), and subthreshold swing (SS) without increasing the device footprint [3], [4]. In this work, by adopting a ~4 nm-thick In 0.53 Ga 0.47 As channel instead of a thick InAs channel, we have further improved the off-state characteristics at high V DS and achieved 81 mV/dec. minimum subthreshold swing (SS min ) for a 35 nm-L g device at V DS =0.5 V and 385 μA/μm on-current (I on ) at 100 nA/μm off-current (I off ) and V DD =0.5 V, which are the best SS min and I on from all reported In 0.53 Ga 0.47 As channel FETs.

Because of the low effective mass, MOSFETs using In-rich (x>53%) In x Ga 1-x As channels [1-5] exhibit high on-state current I on at low drain bias (V DS =0.5 V). However, the small bandgap of high-indium In x Ga 1-x As channels can lead to high off-state leakage I off due to band-to-band tunneling (BTBT) and impact ionization (I.I.). Earlier we had reported [1] that adding an unintentionally-doped (U.I.D.) InGaAs vertical spacer within the raised source/drain (S/D) of an InAs/InGaAs channel MOSFET substantially reduced I off . Here we compare the characteristics of FETs using a wide-bandgap U.I.D. InP vertical spacer to earlier results [1] using an InGaAs spacer, and to control devices using only a very thin spacer. We find that FETs using InP spacers have I off comparable to FETs using narrower-bandgap InGaAs spacers of similar thickness, suggesting that with the spacer, the observed I off at high V DS arises from BTBT or I.I. within the channel, and not within the high-field gate-drain spacer layer. Further, the wide-gap U.I.D. InP source spacer does not increase the threshold voltage V th , suggesting that the gated potential barrier remains in the channel and not in the source spacer region. We also compare the on-state characteristics of FETs using InAs/InGaAs channels and an N+ InP S/D. Unlike the findings of [6], we do not observe improved I on with the use of a wider-bandgap N+ source.

While the growth of III-As and III-P semiconductors is well-established, and their transport properties well-understood, the performance of high-frequency and VLSI electron devices can still be substantially improved. Here we review design principles, experimental efforts, and intermediate results, in the development of nm and THz electron devices, including nm InAs/InGaAs planar MOSFETs and finFETs for VLSI, InGaAs/InP DHBTs for 0.1-1 THz wireless communications and imaging, and ~5nm InAs/InGaAs Schottky diodes for mid-IR mixing.

A monolithic Ku-band phase shifter employing voltage tunable Bi/sub 1.5/Zn/sub 1.0/Nb/sub 1.5/O/sub 7/ (BZN) thin film parallel plate capacitors is reported. BZN films were deposited by radio frequency magnetron sputtering on single-crystal sapphire substrates. A nine-section distributed coplanar waveguide loaded-line phase-shifter structure was designed. A differential phase shift of 175/spl deg/ was achieved with a maximum insertion loss of 3.5 dB at 15 GHz, giving a figure of merit /spl sim/50/spl deg//dB. To the best of our knowledge, this is the first demonstration of a monolithic tunable microwave circuit using BZN thin films.

Oxide-based resistive switching devices are promising candidates for new memory and computing technologies. Poor understanding of the defect-based mechanisms that give rise to resistive switching is a major impediment for engineering reliable and reproducible devices. Here we identify an unintentional interface layer as the origin of resistive switching in Pt/Nb:SrTiO3 junctions. We clarify the microscopic mechanisms by which the interface layer controls the resistive switching. We show that appropriate interface processing can eliminate this contribution. These findings are an important step towards engineering more reliable resistive switching devices., Understanding the resistive switching mechanism in oxide-based memories is an ongoing challenge. Here, the authors isolate an unintentional interfacial layer as the origin of resistive switching in Pt/Nb:SrTiO3 junctions, and show that suitable processing can remove this unwanted contribution.

As FETs are scaled, the dielectric and semiconductor channel thicknesses must be reduced to suppress short-channel effects. Even using fin field effect transistors (finFETs) and gate all around FETs (GAAFETs), [1],[2], whose electrostatic performance is excellent, at 4nm gate length the channel should be less than 2nm thick. To obtain high drive current per unit IC die area, the fin height should be many times the fin pitch, i.e. tens to hundreds of nm. Dry-etching a fin of few-nm width and > 100 nm height presents severe challenges in control of etch sidewall slope and in minimizing surface damage. Here we report an InGaAs finFET fabrication flow which form fins of sub-10nm width and 200 nm height. Fin width is controlled by atomic layer epitaxial (ALE) growth and by semiconductor selective crystallographic wet etching. We further demonstrate self-aligned source-drain regrowth in this process [3],[4]. This facilitates scaling of the source/drain pitch to small dimensions.

Given low interface trap densities and low access resistances, InGaAs MOSFETs can provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT), and are thus strong candidates for use in VLSI.1 Transconductance as high as 2.1 mS/μm (Vds=0.5 V) with 115 mV/decade (Vds=0.5 V) subthreshold swing has been reported2 in planar III-V MOSFETs using a gate recess etch through the N+ InGaAs contact layer. It remains to be established whether the necessary etch depth control can be obtained at VLSI integration scales and 10-20 nm gate lengths. Using self-aligned regrowth of the N+ source and drain, III-V MOSFETs can be fabricated without requiring this gate recess etch;3 1.9 mS/μm (Vd =1 V) with 116 mV/decade (Vds=0.05 V) subthreshold swing was reported in a 55 nm Lg InGaAs MOSFET with MOCVD source-drain regrowth.4 Note that no post-regrowth etching of the channel surface is reported in (4). We have recently found5 that InGaAs MOSFETs using MBE source-drain regrowth, subthreshold swing and transconductance are substantially improved by removing a 5 nm N+ InGaAs channel cap post-regrowth and immediately prior to gate dielectric deposition, suggesting damage to the channel surface during regrowth. Here, we report similar findings for MOCVD regrowth. We fabricated 65 nm Lg In0.53Ga0.47As surface-channel MOSFETs in a gate-last process with self-aligned raised InGaAs S/D access regions formed by MOCVD regrowth. Removal of ~ 2.4 nm of the channel surface by digital etching improved the transconductance from 1.1 to 1.58 mS/μm (65 nm Lg Vd=0.5 V), and reduced the subthreshold swing from 326 to 110 mV/dec (1 μm Lg, Vds=0.05 V). These results suggest that substantial surface damage arises, and must be addressed, in MOCVD regrowth III-V MOSFET processes.

We report on the first high electron density SrTiO3/GdTiO3 (STO/GTO) heterostructure field effect transistors (HFETs). Recently, there has been great interest in high density 2DEGs formed at the interfaces between perovskite oxides [1]. In particular, the STO/GTO interface has been shown to have a sheet charge density of 3 × 1014 cm-2, equivalent to 0.5 e- per unit cell [2], due to the polar discontinuity at the interface (Fig. 2) [3], which is the highest achieved sheet charge density for any semiconductor 2D electron gas (2DEG). The high charge density and the high breakdown strength of these systems make them promising for electronics and plasmonics, as well as for new applications of correlated electron gas systems [4]. In this work, we show for the first time, current modulation in the STO/GTO system, with channel charge modulation of 6×1013 electrons/cm2, which is the highest reported value for any semiconductor material system.

We demonstrate In0.53Ga0.47As surface channel MOSFETs using a gate-last process and MBE source/drain (S/D) regrowth. The structure uses a sacrificial N+ InGaAs channel cap layer between the regrown S/D contact layer and the channel, which is removed in the channel region by a “digital” etch process incorporating UV ozone oxidation and surface stripping in dilute HCl. A device with 65 nm-Lg and 1.2 nm EOT shows 1.6 mS/μm peak transconductance at Vds = 0.5 V and 120 mV/dec SS at Vds = 0.05 V, while 535 nm-Lg devices show 95 mV/dec SS at at Vds = 0.1 V.

Amorphous LaAlO3 thin films have been deposited by molecular beam deposition directly on silicon without detectable oxidation of the underlying substrate. We have studied these abrupt interfaces by Auger electron spectroscopy, high-resolution transmission electron microscopy, medium-energy ion scattering, transmission infrared absorption spectroscopy, and x-ray photoelectron spectroscopy. Together these techniques indicate that the films are fully oxidized and have less than 0.2 A of SiO2 at the interface between the amorphous LaAlO3 and silicon. These heterostructures are being investigated for alternative gate dielectric applications and provide an opportunity to control the interface between the silicon and the gate dielectric. (C) 2004 American Institute of Physics.

There has been much interest in the injection and detection of spin polarized carriers in semiconductors for the purposes of developing novel spintronic devices. Here we report the electrical injection and detection of spin-polarized carriers into Nb-doped strontium titanate (STO) single crystals and La-doped STO epitaxial thin films using MgO tunnel barriers and the three-terminal Hanle technique. Spin lifetimes of up to ~100 ps are measured at room temperature and vary little as the temperature is decreased to low temperatures. However, the mobility of the STO has a strong temperature dependence. This behavior and the carrier doping dependence of the spin lifetime suggest that the spin lifetime is limited by spin-dependent scattering at the MgO/STO interfaces, perhaps related to the formation of doping induced Ti3+. Our results reveal a severe limitation of the three-terminal Hanle technique for measuring spin lifetimes within the interior of the subject material., Comment: 13 pages, 6 figures

Parallel plate capacitors with quality factors exceeding 1000 were fabricated using Ba0.3Sr0.7TiO3 (BST) thin films grown by hybrid molecular beam epitaxy on epitaxial Pt bottom electrodes. The influence of film stoichiometry was investigated by varying the (Ba + Sr)/Ti ratio around the stoichiometric composition. The quality factor is highest for stoichiometric films, but (Ba + Sr)-rich films can be biased to higher fields. Furthermore, two different processes were used to deposit the top electrodes of the parallel plate capacitors. While the quality of the top contact/BST interface did not strongly affect the device quality factor, an enhancement in the dielectric tunability was seen for capacitors with top electrodes deposited at high temperatures, which effectively removes interfacial contamination layers.

The fabrication, measurement, and modeling of radio-frequency (RF), tunable interdigital capacitors (IDCs) are described. High quality factors of 200 in the S/L-bands combined with a 47% tunability are achieved by utilizing epitaxial (Ba,Sr)TiO3 films grown by hybrid molecular beam epitaxy on LaAlO3 substrates. The fabricated devices consisted of one-port and two-port IDCs embedded in ground-signal-ground, coplanar waveguide transmission lines to enable RF probing. Wideband RF scattering parameters under bias were measured from 100 MHz to 40 GHz. A commutation quality factor averaging 6000 across the L band is achieved. These are the highest reported values in this band.

Solid-state modulation of 2-dimensional electron gases (2DEGs) with extreme (∼3.3 × 1014 cm−2) densities corresponding to 1/2 electron per interface unit cell at complex oxide heterointerfaces (such as SrTiO3/GdTiO3 or SrTiO3/SmTiO3) is challenging because it requires enormous gate capacitances. One way to achieve large gate capacitances is by geometrical capacitance enhancement in fin structures. In this work, we fabricate both Au-gated planar field effect transistors (FETs) and Fin-FETs with varying fin-widths on 60 nm SrTiO3/5 nm SmTiO3 thin films grown by hybrid molecular beam epitaxy. We find that the FinFETs exhibit higher gate capacitance compared to planar FETs. By scaling down the SrTiO3/SmTiO3 fin widths, we demonstrate further gate capacitance enhancement, almost twice compared to the planar FETs. In the FinFETs with narrowest fin-widths, we demonstrate a record 2DEG electron concentration modulation of ∼2.4 × 1014 cm−2.