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In this article the recent progress in the elements of EUV lithography is presented. Source power around 205W was demonstrated and further scaling up is going on, which is expected to be implemented in the field within 2017. Source availability keeps improving especially due to the introduction of new droplet generator but collector lifetime needs to be verified at each power level. Mask blank defect satisfied the HVM goal. Resist meets the requirements of development purposes and dose needs to be reduced further to satisfy the productivity demand. Pellicle, where both the high transmittance and long lifetime are demanded, needs improvements especially in pellicle membrane. Potential issues in high-NA EUV are discussed including resist, small DOF, stitching, mask infrastructure, whose solutions need to be prepared timely in addition to high-NA exposure tool to enable this technology.

Abrupt changes in sidewall profile were induced in pulsed plasma etch process for high aspect ratio isolation trench structuring. Impacts of operational parameters when applying pulsed RF bias power were investigated. Silicon sidewall chipping problems were removed mainly by increasing bias power level and pulse frequency. The chemical sensitivity of O2 has shown decreased in extremely narrow trench spaces of high pattern density

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (Vth), Vth drift, high resistance state (RESET) resistance (RRESET) drift, and crystallization temperature (Tcrys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. Vth scales down to 0.65-0.5 V (at 25°C-75°C) for 6-nm-thick Ge2Sb2Te5 (GST), showing that stable read operation is possible in scaled PCM devices. The Vth drift measurement suggests that Vth drift can be attributed to threshold switching field (Eth) drift, whereas Vth0, i.e., Vth at zero thickness, stays almost constant. RRESET drift shows no dependence on the amorphous GST thickness. Tcrys is ~175°C for the device with 6-nm-thick GST, compared with ~145°C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM.

We studied the misalignment between active and gate layer in terms of silicon dislocation caused by high temperature anneal process in SOG based STI gap-fill process. The SOG process is one of good candidates to overcome gap-fill limitation due to its excellent gap-fill characteristics. However, the SOG process needs high temperature anneal process to convert from Si-H, N-H to Si-O bond, which leads to the misalignment due to large stress change. We suggest that silicon defect is generated from ion bombardment at trench etch process and accelerated from hysteresis at anneal process. The O2 cure process is known as one of feasible methods to cure silicon damage through recrystallization. Based on this model, the misalignment was significantly improved as removing the defect through O2 cure process following trench etch process.

High-k dielectrics like Ta2O5, TiO2 etc. should overcome high leakage current due to the low energy band-gap property for applying to the future DRAM device below 50nm design rule beyond. Various techniques including metal doping and bi-layer scheme were studied to improve the leakage current of I-V characteristics. The leakage current of Dy or Zr doped TiO2 could be improved depending on the doping concentration. Nb doping in Ta2O5 could increase the dielectric constant within the appropriate level of leakage current at the operation voltage. Bi-layer scheme of high-k dielectrics like HfO2-TiO2 or ZrO2-TiO2 also applied to reduce the leakage current with the high work function Ru electrode. Combination of high work function Ru as a top electrode with the bottom TiN electrode could reduce the leakage current by increasing band offset at the interface between the high-k and the electrode.

In this letter, a cost-effective vertical diode scheme for next-generation memory devices, including phase-change memories (PCMs), is realized. After the contact formation for diodes with only one mask layer, an amorphous silicon (a-Si) film was deposited within the contacts using SiH4 ramp-up ambient in a conventional batch-type furnace in order to minimize the growth of native oxide. A deposition/etch-back/deposition scheme enabled us to achieve robust vertical diodes without any seams or interfacial oxide layer within the vertical diode pillars. Subsequent annealing at 600 °C provided solid-phase epitaxial alignment of the a-Si layer. An ideality factor revealed that the new scheme provided noticeable crystallinity of the silicon diodes. Moreover, the electrical characteristics of the diodes verified that the scheme was suitable for full operation of PCM devices.

We first present chemical-vapor-deposited GeBiTe (CVD GBT) in a confined cell for high-performance phase-change random access memory (PRAM). Due to the fast crystallization of GBT, we were able to reduce the speed to less than 26 ns while maintaining endurance characteristics up to 109 cycles. Our results indicate that the scalable PRAM device enabling the use of PRAM in dynamic RAM and storage class memory applications can be realized using CVD GBT.

In this paper, current-voltage-temperature (I-V-T) characteristics of vertical diodes realized by different selective epitaxial growth techniques have been investigated. Diodes by the batch-type cyclic SEG process at low temperature have shown eligible performances for vertical switches, including ideality factor of 1.08, off-current of 1.0×10−12 A and on/off-ratio of 2.4×108. The optimization of crystallographic defects and series resistance is expected to be the most critical for the performances of vertical diodes for next generation memories.

Flowable CVD (Chemical Vapor Deposition) process having merits in terms of both superior gap-fill performance of SOD (Spin-on Dielectric) and process stability of CVD was introduced for the interlayer dielectric (ILD) in sub-20nm devices based on new concept and precursor. Remote plasma during low temperature deposition and ozone treatment was adopted to stabilize the film. We also developed a novel Flowable CVD process which does not oxidize Si or electrode, resulted in removal of Si 3 N 4 stopper layer as an oxidation or diffusion barrier. After the application of Flowable CVD to 20nm DRAM ILD, we could reduce not only loading capacitance of Bit-line by 15% but also enhance comparable productivity. Through the successful development of sub-20nm DRAM ILD Gap-fill process, Flowable CVD was successful demonstrated as a promising candidate for mass production-worthy ILD in sub-20nm next generation devices.

Data retention characteristic is one of the most critical issues in low power DRAMs because it determines idle currents of self-refresh operation. Compared to normal healthy cells, a few ppm orders of cells in a tail distribution have much higher leakage currents. The origin of the leaky cells (so called weak cells or tail cells) has been quite arguable for the past decades [1, 2], but it should be scrutinized in order to achieve long data retention time. In this paper, we have thoroughly investigated the behavior of the retention weak cells using a newly generated combination program and TEM analysis so as to discover and explain their origins

To improve the IPD reliability of NAND flash memory, plasma oxidation was introduced as the post-treatment process of ONO (Oxide/Nitride/Oxide) IPD. The LP-CVD SiO2 modified by plasma oxidation showed the excellent electrical properties. e.g., low leakage current, high breakdown voltage etc. By the analysis of Tof-SIMS and XRR, we could observe the several changes of physical characteristics such as the reduction of impurities (H, N etc.), the increase of oxide density, and the improvement of oxide surface roughness. We found out the appropriate treatment condition to be able to densify oxide layer without the addition of ONO Equivalent Oxide Thickness (EOT). The LP-CVD SiO2 prepared by plasma oxidation was used for the ONO IPD of 50nm NAND flash device and also compared with the conventional LP-CVD SiO2 in the aspect of the IPD reliability.

We studied factors which affect cell Vth variation in the floating gate flash memory. By simulation and experiment, we showed that the shape of STI (shallow trench isolation) and the tunnel oxide thickness in the STI edge were the main control factors. For example, sharp and thin oxide in the STI edge caused an uncontrolled F-N gate current in the program or erase operation, which directly indicated the amount of threshold voltage in the flash memory. Furthermore, we found that tunnel oxide thinning was closely related to the activation energy in the oxidation process. Smaller activation energy resulted in better thinning and better cell Vth distribution.