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We report the design, fabrication and characterization of a 1.55-μm dual-wavelength Distributed Bragg Reflector (DBR) laser photonic integrated circuit (PIC) chip for continuous-waves (CW) terahertz generation. The PIC chip consists of a pair of parallel DBR lasers with integrated semiconductor optical amplifiers (SOA), and a multimode interference (MMI) coupler for combining the two wavelength channels into a single output waveguide. A room temperature continuous wave THz tuning range of 0.06 THz – 0.71 THz was obtained through optical heterodyne technique.

On chip waveguide optical amplifiers have been extensively studied over the last years, with a wide variety of materials tested and proposed for different applications. Among the most prominent solutions for on-chip amplification, erbium doped waveguide amplifiers (EDWAs) are able to offer attractive performance metrics that can exceed SOA-based amplification solutions in traditional single and multi-channel systems. In this letter, we experimentally demonstrate a record high $8\times 40$ Gbps non return to zero (NRZ) wavelength division multiplexing (WDM) data amplification through a 5.9 cm long on-chip amplifier consisting of an erbium-doped aluminum oxide spiral waveguide monolithically integrated on the Si3N4 platform. Experimental results show more than 12.7 dB amplification per channel for low saturation total input power of −2.75 dBm, and clear eye diagrams and bit-error rate values below the KR4-FEC limit of $2\times 10 ^{-5}$ for all eight channels without any digital signal processing (DSP) applied to the signal to the receiver or transmitter side. The high losses from the fiber to chip interfaces, however, prevented achieving device net gain.

We report a widely tunable V-cavity laser monolithically integrated with an electro-absorption modulator (EAM). The device shows a 41-nm wavelength tunability covering 51 channels at 100 GHz spacing on the ITU grid, with a side-mode suppression ratio (SMSR) higher than 47 dB. Error-free transmission over 50 km standard single-mode fiber at 10 Gb/s is demonstrated at all wavelengths over the tuning range. The integrated EAM exhibits a dynamic extinction ratio higher than 12.5 dB. The bit-error-rate measurements show a power penalty less than 3 dB for 50-km transmission. The results demonstrate that this ultra-compact and regrowth-free electro-absorption modulated tunable laser can be a cost-effective transmitter solution for DWDM metropolitan and access networks.

The developed double-layer Al 2 O 3 -Si 3 N 4 photonic platform monolithically combines the outstanding optical features of LPCVD Si 3 N 4 and the properties of rare-earth-ion-doped Al 2 O 3 active material. In this letter, a resonant coupling is studied in Al 2 O 3 -Si 3 N 4 couplers by introducing a lateral shift between a lateral Al 2 O 3 taper and a vertical Si 3 N 4 taper. The proposed resonant couplers enable to reduce mode mismatch losses at the taper tips, avoiding submicrometer lithography process while yielding a broadband and fabrication-tolerant performance. Undoped Al 2 O 3 -Si 3 N 4 resonant couplers are fabricated, with measured total losses less than 0.18 dB in the 1460-1635-nm spectral window. The first demonstration of active-passive integration is carried out using resonant couplers between Al 2 O 3 :Er 3+ and Si 3 N 4 waveguides, showing the great potential of our double-layer Al 2 O 3 -Si 3 N 4 platform for the realization of active-passive-integrated functionalities in the Si 3 N 4 technology.

AlGaN/GaN E/D-mode GaN inverters are successfully fabricated on a 150-mm Si wafer. P-GaN gate technology is applied to be compatible with the commercial E-mode GaN power device technology platform and a systematic study of E/D-mode GaN inverters has been conducted with detail. The key electrical characters have been analyzed from room temperature (RT) to 200 °C. Small variations of the inverters are observed at different temperatures. The logic swing voltage of 2.91 V and 2.89 V are observed at RT and 200 °C at a supply voltage of 3 V. Correspondingly, low/high input noise margins of 0.78 V/1.67 V and 0.68 V/1.72 V are observed at RT and 200 °C. The inverters also demonstrate small rising edge time of the output signal. The results show great potential for GaN smart power integrated circuit (IC) application.

In this work, normally-off p-channel and n-channel heterojunction field-effect transistors (HFETs) were fabricated based on a p-GaN gate Al0.2Ga0.8N/Al0.05Ga0.95N HFET platform. For p-channel HFETs, normally-off operation and low gate leakage were obtained by using a recessed-gate structure and a 20 nm Al2O3 thin film grown by thermal atomic layer deposition as the gate insulator. The normally-off p-channel HFETs exhibited a threshold voltage of 105. By introducing an Al0.05Ga0.95N channel instead of a conventional GaN channel layer, the threshold voltage increased from 1.1 V to 1.5 V and the breakdown voltage almost doubled from 270 to 580 V for n-channel HFETs. These results indicate that n-channel and p-channel HFETs based on p-GaN/Al0.2Ga0.8N/Al0.05Ga0.95N heterostructures have a great potential for monolithic integration.

In this paper, we demonstrate InGaAs FinFETs 3-D sequentially (3DS) integrated on top of a fully depleted silicon-on-insulator CMOS. Top layer III–V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. We demonstrate that the low thermal budget of the top layer process does not affect the lower level FETs performance. An on-current of $200~\mu \text{A}/\mu \text{m}$ (at $I_{\mathrm{ OFF}} = 100$ nA/ $\mu \text{m}$ and $V_{\mathrm{ DD}} = 0.5$ V) is achieved, representing the highest reported for 3DS integrated III–V FETs on silicon, showing a 50% improvement in $R_{\mathrm{ ON}}$ compared to previous work. The achieved improved performance can be attributed to the introduction of spacers, doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.

VTT's 3 μm SOI platform with record low propagation loss (0.1 dB/cm for fundamental mode), as well as polarization insensitivity, offers a rich portfolio of efficient passive and active components. With a view to extend the component toolbox by monolithically integrating high-speed plasmonic modulators, we have developed an a-Si:H based waveguide escalator to take out light from highly confined thick-SOI passives to the top layer where active materials are monolithically integrated. Using the compact escalator, monolithic integration of various high-speed active components on the 3 μm SOI platform are proposed.

Dynamically reconfigurable passive optical networks (PONs) using time-division multiplexing and dense wavelength division multiplexing will require low-cost, high-performance customer premises equipment to be economically viable. In particular, substantial cost savings can be achieved through the use of efficient re-growth free, foundry-compatible fabrication techniques. Using this strategy, this paper presents the first detailed characterization of a monolithically integrated transmitter comprised of a discretely tunable slotted Fabry–Pérot ridge waveguide laser, an absorptive modulator and a semiconductor optical amplifier (SOA) produced using a standard off-the-shelf AlInGaAs/InP multiple quantum well epitaxial structure. This first generation device demonstrates a discrete single-mode tuning range of approximately 12 nm between 1551nm and 1563 nm with a side-mode suppression ratio ≥30 dB. Moreover, the integrated modulator section is shown to support transmission at 10 Gb/s using non-return to zero on-off keying with an extinction ratio in excess of 8 dB. Furthermore, using a time-resolved chirp measurement technique to examine dynamic deviations in the set carrier frequency, the modulator section exhibits a chirp contribution of

International audience; The formation and propagation of anti-phase boundaries (APBs) in the epitaxial growth of III-V semiconductors on Silicon is still the subject of great debate, despite the impressive number of studies focusing on this topic in the last past decades. The control of the layer phase is of major importance for the future realization of photonic integrated circuits that include efficient light sources or for new nano-electronic devices, for example. Here, it is experimentally demonstrated that the main-phase domain overgrows the anti-phase domains (APDs) because it grows faster. A large-scale analysis of the phase evolution based on reflection high-energy electron diffraction and atomic force microscopy in the case of the molecular beam epitaxy of GaSb on Silicon (001) substrate is presented. The growth rate difference between the two domains is accurately measured and is shown to come from the atomic step distribution at the III-V surface. The influence of the substrate preparation as well as of the growth condition on this distribution is also clarified.

A three-section distributed feedback laser with a 2.5 InP/air pair of distributed Bragg reflectors (DBRs) was fabricated and analyzed in terms of its microwave generation capability. A widely tunable single radio frequency (RF) signal can be detected using optical heterodyning, and the tuning range is from 2 to 45 GHz. The incorporation of the third section provides an opportunity to present the dual RF operation when three emission peaks are near to each other in the wavelength domain. The proposed design provides a 21.3% enhancement in the RF tuning range compared with the range of a two-section laser (35.29 GHz versus 42.81 GHz). The compactness of the proposed device can be useful for future radio-over-fiber applications.

Low-cost, high-performance integration technologies are instrumental for active–passive integrated photonics devices. The monolithic integration of Al2O3 and Si3N4 is studied, enabling to combine the promising optical features of Si3N4 with the excellent optical gain characteristics of rare-earth-ion doped Al2O3. The Al2O3 and Si3N4 layers are separated by a thin SiO2 film and coupled by adiabatically width-tapered Al2O3 and thickness-tapered Si3N4 waveguides. In this paper, a detailed characterization of the couplers, as well as a study of the influence of the different design parameters and fabrication tolerances on the final device performance is presented. Test structures are characterized under transverse electric (TE) polarization. Measured loss per coupler is as low as 0.26 ± 0.03 dB at the wavelength of 1030 nm, and below 0.24 dB in the spectral window of 1460–1635 nm. Lateral misalignment of ±1 μ m results in less than 0.6 dB increase of the coupler loss at 1030 nm, and the tolerance of misalignment goes up to 1.7 μ m at the investigated longest wavelength of 1635 nm without introducing extra coupler losses. The reported integration technology paves the way toward a double-layer platform monolithically integrating Si3N4 and rare-earth-ion doped Al2O3 for active–passive photonic functionalities.

We present a single-photon sensor based on the single-photon avalanche diode (SPAD) that is suitable for low-cost and low-voltage light detection and ranging (LiDAR) applications. It is implemented in a zero-change standard 0.18-&mu, m complementary metal oxide semiconductor process at the minimum cost by excluding any additional processing step for customized doping profiles. The SPAD is based on circular shaped P+/N-well junction of 8-&mu, m diameter, and it achieves low breakdown voltage below 10 V so that the operation voltage of the single-photon sensor can be minimized. The quenching and reset circuit is integrated monolithically to capture photon-generated output pulses for measurement. A complete characterization of our single-photon sensor is provided.

Ultraviolet (UV) light plays an important role in air/water/surface sterilization now. Maintaining a certain light intensity is often required to attain the targeted effect. In this paper, on-chip power monitoring of a UV-A light-emitting diode (LED) via sapphire substrate is reported. A p&ndash, i&ndash, n photodiode loop that surrounds the UV-A LED was designed and fabricated to monitor the output power by detecting the scattered light of the LED propagating through the sapphire substrate. No particular waveguide structure or processing parameter control was needed. The monitoring responsivities per unit of surface-emitting power obtained were approximately 21 and 25 mA/W at photodiode biases of 0 and 3 V, respectively. When combined with a transimpedance amplifier, a monitoring responsivity of 1.87 V/mW at zero bias was measured, and a different monitoring responsivity could be customized by adjusting the gain of the transimpedance amplifier. The operation principle of this device might be applicable to UV-B or UV-C LEDs.

Data usage continues to rise exponentially with user demand, and the bandwidth of optical communications is reaching its limit. Spectrally efficient advanced modulation formats are being used to increase the data rate within the existing bandwidth. Mach-Zehnder Modulators achieve high spectral density by modulating both the phase and amplitude of light. At the moment, laser light sources and Mach-Zehnder Modulators are built discretely and packaged and coupled thereafter. Photonic Integrated Circuits (PICs) place multiple photonic components onto single chips, with the benefit of compactness resulting in lower cost through simpler coupling, lower power consumption, and volume manufacture. The difficulty faced by photonic integration is that different components require different material for their different functions, and so cannot be easily placed onto the same material substrate wafer. Existing methods use regrowth techniques to selectively replace material around the chip, but regrowth is expensive and time consuming. This work vertically integrated a passive waveguide above an active waveguide using regrowth-free monolithic integration. The passive and active waveguides are designed for Mach-Zehnder modulator and laser material. The waveguides were processed on an InP platform, and consisted of AlGaInAs alloys. To our knowledge this is the first time a passive waveguide has been vertically integrated above an active waveguide for III-V semiconductors, and the first time two AlGaInAs waveguides have been vertically integrated, using monolithic regrowth-free techniques on InP. Vertical coupling was performed through lateral tapers, and an isolation barrier between the stacked waveguides allows the vertical integration of already optimised discrete components without modification. As the isolation barrier deliberately reduces the coupling between the waveguides away from the transition region, a technique using a third passive waveguide in the barrier was used to increase the vertical coupling while maintaining isolation. A regrowth-free vertical monolithic PIC was conceived, designed, grown, fabricated and tested to prove its operation. The two vertically stacked waveguides provide a solution for integrating active and passive material, so that a laser and Mach-Zehnder Modulator can be monolithically integrated to create a low cost advanced modulator to meet today’s ever increasing data demands.

A monolithic BiCMOS-plasmonic transmitter offering 120 GBd NRZ-OOK is demonstrated. The chip comprises an electronic-photonic layer stack. The SiGe BiCMOS electrical layers offer PRBS generation and 4:1 power multiplexing, while the plasmonic layer offers electro-optical modulation at highest speed., 45th European Conference on Optical Communication (ECOC 2019), ISBN:978-1-83953-185-9

A prominent nonlinear optical phenomenon that is extensively studied using nanostructured materials is second-harmonic generation (SHG) as it has applications in various fields. Achieving efficient...

Recent developments in multispectral cameras have demonstrated how compact and low-cost spectral sensors can be made by monolithically integrating filters on top of commercially available image sensors. In this paper, the fabrication of a RGB + NIR variation to such a single-chip imaging system is described, including the integration of a metallic shield to minimize crosstalk, and two interference filters: a NIR blocking filter, and a NIR bandpass filter. This is then combined with standard polymer based RGB colour filters. Fabrication of this chip is done in imec’s 200 mm cleanroom using standard CMOS technology, except for the addition of RGB colour filters and microlenses, which is outsourced.

The article reviews the current status of label-free integrated optical sensors focusing on the evolution over the years of their analytical performance. At first a short introduction to the evanescent wave optics is provided followed by detailed description of the main categories of label-free optical sensors including sensors based on surface plasmon resonance (SPR), grating coupler, photonic crystals, ring resonators and interferometric transducers. After a short reference to SPR techniques, including localized SPR, integrated optical sensors i.e., grating-couplers, interferometers, photonic crystals, microring resonators are reviewed. For each type of sensor, the detection principle is first provided followed by description of the different transducer configurations so far developed and their performance as biosensors. Finally, a short discussion about the current limitations and future perspectives of integrated label-free biosensors optical sensors is provided

Direct integration of III–V light emitting sources on Si substrates has attracted significant interest for addressing the growing limitations for Si-based electronics and allowing the realization of complex optoelectronics circuits. However, the high density of threading dislocations introduced by large lattice mismatch and incompatible thermal expansion coefficient between III–V materials and Si substrates have fundamentally limited monolithic epitaxy of III–V devices on Si substrates. Here, by using the InAlAs/GaAs strained layer superlattices (SLSs) as dislocation filter layers (DFLs) to reduce the density of threading dislocations. We firstly demonstrate a Si-based 1.3 µm InAs/GaAs quantum dot (QD) laser that lases up to 111 °C, with a low threshold current density of 200 A/cm2 and high output power over 100 mW at room temperature. We then demonstrate the operation of InAs/GaAs QD superluminescent light emitting diodes (SLDs) monolithically grown on Si substrates. The fabricated two-section SLD exhibits a 3 dB linewidth of 114 nm, centered at ～1255 nm with a corresponding output power of 2.6 mW at room temperature. Our work complements hybrid integration using wafer bonding and represents a significant milestone for direct monolithic integration of III–V light emitters on Si substrates.

A technique to locally grow germanium-on-insulator (GOI) structure on silicon (Si) platform is studied. On (001) Si wafer, silicon dioxide (SiO2) is thermally grown and patterned to define growth window for germanium (Ge). Crystalline Ge is grown via selective hetero-epitaxy, using SiO2 as growth mask. Lateral overgrowth of Ge crystal covers SiO2 surface and neighboring Ge crystals coalesce with each other. Therefore, single crystalline Ge sitting on insulator for GOI applications is achieved. Chemical mechanical polishing (CMP) is performed to planarize the GOI surface. Transmission electron microscopy (TEM) analysis, Raman spectroscopy, and time-resolved photoluminescence (TRPL) show high quality crystalline Ge sitting on SiO2. Optical response from metal-semiconductor-metal (MSM) photodetector shows good optical absorption at 850 nm and 1550 nm wavelength. © 2015 Elsevier B.V. All rights reserved.

The InSb photodetector on a Si substrate acts as a signal receiver for the mid-infrared silicon photonics application to overcome the limitation of group IV semiconductors. In this paper, we demonstrated an InSb p–i–n photodetector with an InAlSb barrier layer grown on (100) silicon substrates via a GaAs/Ge buffer by molecular beam epitaxy. The lattice mismatch between InSb and GaAs was accommodated by an interfacial misfit array. The 50% cutoff detectable wavelength of this detector increased from 5.7 μm at 80 K to 6.3 μm at 200 K. An 80 K detectivity of 8.8 × 109 cmHz1/2 W–1 at 5.3 μm was achieved with a quantum efficiency of 16.3%. The dark current generating mechanism of this detector is both generation–recombination and surface leakage above 140 K, while it is only surface leakage from 120 to 40 K. NRF (Natl Research Foundation, S’pore) Accepted version

© 2018 IEEE. The integration of infrared sensitive thin-film materials with solution processing capabilities on top of Si substrates is a significant step towards cost-efficient infrared imagers. Colloidal quantum dots based on lead sulfide are very attractive materials for the realization of novel image sensors combining low cost synthesis and processing with deposition over large area and on any substrate. The tunable band gap enables selective detection in wavelengths ranging from the visible up to the short-wave-infrared (SWIR). This work describes the first results of a roadmap that will enable the integration of quantum dot photodiodes (QDPD) on top of a Si based CMOS read-out circuit. Photodiodes using an n-p junction architecture are fabricated on Si substrates, showing low dark current of 30 nA/cm 2 at -1 V reverse bias, EQE above 20% and specific detectivity higher than 1012cm Hz1/2 W-1 at the wavelength of 940 nm. Efficiency is improved by tuning the top contact transparency with optical modeling. Furthermore, photolithographic patterning of the thin-film stack is introduced for the first time, showing the feasibility of pixel pitches down to 40μ, opening the way towards high resolution monolithic infrared imagers and the incorporation of infrared sensitive pixels next to visible ones. ispartof: pages:508-511 ispartof: 2018 IEEE SENSORS vol:2018-October pages:508-511 ispartof: 17th IEEE SENSORS Conference location:INDIA, New Delhi date:28 Oct - 31 Oct 2018 status: published

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10(-6) A/cm(2) at 2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

The paper addresses a top-down design flow of depletion-load digital inverter formed by monolithically integrated depletion-mode and enhancement-mode high electron mobility transistors (HEMTs) on common InAlN/GaN heterostructure grown on sapphire substrate. We describe the inverter design at transistor level using HSPICE models developed earlier. The inverter layout representation, which also defines the lithographic masks required for the fabrication process, is presented as well. The proposed mask set was designed taking into account the design-for-manufacturing approach. Furthermore, we evaluated measured properties and performance of the fabricated transistors and circuits and recalibrate the transistor models according to the latest measurements.

Si3N4 grown by low pressure chemical vapor deposition (LPCVD) on thermally oxidized silicon wafers is largely utilized for creating integrated photonic devices due to its ultra-low propagation loss and large transparency window (400 nm to 2350 nm). In this paper, an ultra-low-loss and broadband mode converter for monolithic integration of different materials onto the passive Si3N4 photonic technology platform is presented. The mode size converter is constructed with a vertically tapered Si3N4 waveguide that is then buried by a polymer or an Al2O3 waveguide. The influence of the various design parameters on the converter characteristics are investigated. Optimal designs are proposed, in which the thickness of the Si3N4 waveguide is tapered from 200 nm to ~40 nm. The calculated losses of the mode converters at 976 nm and 1550 nm wavelengths are well below 0.1 dB for the Si3N4-polymer coupler and below 0.3 dB for the Si3N4-Al2O3 coupler. The preliminary experimental results show good agreement with the design values, indicating that the mode converters can be utilized for the low-loss integration of different materials.

We present a method for monolithically integrating mismatched semiconductor materials with Si, coined three-dimensional (3D) heteroepitaxy. The method comprises the replacement of conventional, continuous epilayers by dense arrays of strain- and defect-free, micron-sized crystals. The crystals are formed by a combination of deep-patterning of the Si substrates and self-limited lateral expansion during the epitaxial growth. Consequently, the longstanding issues of crack formation and wafer bowing can be avoided. Moreover, threading dislocations can be eliminated by appropriately choosing pattern sizes, layer thicknesses and surface morphology, the latter being dependent on the growth temperature. We show this approach to be valid for various material combinations, pattern geometries and substrate orientations. We demonstrate that Ge crystals evolve into perfect structures away from the heavily dislocated interface with Si, by using a synchrotron X-ray beam focused to a spot a few hundred nanometers in size and by recording 3D reciprocal space maps along their height. Room temperature photoluminescence (PL) experiments reveal that the interband integrated PL intensity of the Ge crystals is enhanced by almost three orders of magnitude with respect to that of Ge epilayers directly grown on flat Si substrates. Electrical measurements performed on single heterojunction diodes formed between 3D Ge crystals and the Si substrate exhibit rectifying behavior with dark currents of the order of 1 mA/cm2. For GaAs the thermal strain relaxation as a function of pattern size is similar to that found for group IV materials. Significant differences exist, however, in the evolution of crystal morphology with pattern size, which more and more tends to a pyramidal shape defined by stable {111} facets with decreasing width of the Si pillars. © 2013 Elsevier B.V.

In this paper, a monolithic tri-axis piezoresistive high-shock accelerometer has been proposed that has been single-sided fabricated in a single (111)-silicon wafer. A single-cantilever structure and two dual-cantilever structures are designed and micromachined in one (111)-silicon chip to detect Z-axis and X-/Y-axis high-shock accelerations, respectively. Unlike the previous tri-axis sensors where the X-/Y-axis structure was different from the Z-axis one, the herein used similar cantilever sensing structures for tri-axis sensing facilitates design of uniform performance among the three elements for different sensing axes and simplifies micro-fabrication for the multi-axis sensing structure. Attributed to the tri-axis sensors formed by using the single-wafer single-sided fabrication process, the sensor is mechanically robust enough to endure the harsh high-g shocking environment and can be compatibly batch-fabricated in standard semiconductor foundries. After the single-sided process to form the sensor, the untouched chip backside facilitates simple and reliable die-bond packaging. The high-shock testing results of the fabricated sensor show linear sensing outputs along X-/Y-axis and Z-axis, with the sensitivities (under DC 5 V supply) as about 0.80&ndash, 0.88 &mu, V/g and 1.36 &mu, V/g, respectively. Being advantageous in single-chip compact integration of the tri-axis accelerometers, the proposed monolithic tri-axis sensors are promising to be embedded into detection micro-systems for high-shock measurement applications.

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4)O3−δ and polycrystalline (CeY2)Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2)Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates., National Science Foundation (U.S.). Division of Materials Research (Grant No. DMR 0604430), National Science Foundation (U.S.). Division of Materials Research (Grant No. 1231392, Electronic, Photonic, and Magnetic Devices Program)

© 2017 IEEE. Monolithic integration of a half bridge on the same GaN-on-Si wafer is very challenging because the devices share a common conductive Si substrate. In this letter, we propose to use GaN-on-SOI (siliconon- insulator) to isolate the devices by trench etching through the GaN/Si(111) layers and stopping in the SiO2 buried layer. By well-controlled epitaxy and device fabrication, high-performance 200 V enhancement-mode (e-mode) p-GaN high electronmobility transistors with a gatewidth of 36 mm are achieved. This letter demonstrates that by using GaN-on-SOI in combination with trench isolation, it is very promising to monolithically integrate GaN power systems on the same wafer to reduce the parasitic inductance and die size. ispartof: IEEE Electron Device Letters vol:38 issue:7 pages:918-921 status: published

The epitaxial integration of highly heterogeneous material systems with silicon (Si) is a central topic in (opto-)electronics owing to device applications. InP could open new avenues for the realization of novel devices such as high-mobility transistors in next-generation CMOS or efficient lasers in Si photonics circuitry. However, the InP/Si heteroepitaxy is highly challenging due to the lattice (∼8%), thermal expansion mismatch (∼84%), and the different lattice symmetries. Here, we demonstrate the growth of InP nanocrystals showing high structural quality and excellent optoelectronic properties on Si. Our CMOS-compatible innovative approach exploits the selective epitaxy of InP nanocrystals on Si nanometric seeds obtained by the opening of lattice-arranged Si nanotips embedded in a SiO2 matrix. A graphene/InP/Si-tip heterostructure was realized on obtained materials, revealing rectifying behavior and promising photodetection. This work presents a significant advance toward the monolithic integration of graphene/III-V based hybrid devices onto the mainstream Si technology platform.

We describe the development and optical characterization of a planar medium infrared (mid-IR) InSb photodetector on a GaAs substrate technology, capable of integrating MESFETs, to demonstrate a new active pixel device architecture. Our results pave the way for the development of integrated mid-IR focal plane array circuits on a single chip. Device structures with areas down to 0.0016 mm $^{{ {2}}}$ were investigated. By deploying a silicon nitride passivation layer, we were able to reduce leakage current in reverse bias by up to 27% to yield an improved rectifier. Extensive optical characterization was carried out in the near- and mid-IR wavelength range. Responsivities of up to 3.54 A/W and quantum efficiency values above unity were obtained in the near-IR range as a consequence of illumination above the bandgap causing impact ionization. In the mid-IR range, responsivities of up to 0.97 A/W were observed. The bandwidth of the devices proved compatible with video-rate standard sampling rates.

A low-power silicon photonic disk resonator is monolithically and two-dimensionally integrated with complementary metal-oxide-semiconductor (CMOS) electronics. The results show direct integration with established CMOS manufacturing lines without changing either the CMOS or the photonic process stack. Comparable results for each integration method show subpicojoule per bit modulation and the potential for further reductions. The analysis reveals that the process of integration does not limit the performance of photonic or electronic components, and clear steps to use smaller drivers to achieve sub-50 fJ/bit at 10 Gb/s operation are available.

Micro-light-emitting diodes (micro-LEDs) are the key to next-generation display technology. However, since the driving circuits are typically composed of Si devices, numerous micro-LED pixels must be transferred from their GaN substrate to bond with the Si field-effect transistors (FETs). This process is called massive transfer, which is arguably the largest obstacle preventing the commercialization of micro-LEDs. We combined GaN devices with emerging graphene transistors and for the first-time designed, fabricated, and measured a monolithic integrated device composed of a GaN micro-LED and a graphene FET connected in series. The p-electrode of the micro-LED was connected to the source of the driving transistor. The FET was used to tune the work current in the micro-LED. Meanwhile, the transparent electrode of the micro-LED was also made of graphene. The operation of the device was demonstrated in room temperature conditions. This research opens the gateway to a new field where other two-dimensional (2D) materials can be used as FET channel materials to further improve transfer properties. The 2D materials can in principle be grown directly onto GaN, which is reproducible and scalable. Also, considering the outstanding properties and versatility of 2D materials, it is possible to envision fully transparent micro-LED displays with transfer-free active matrices (AM), alongside an efficient thermal management solution.

ispartof: IEICE ELECTRONICS EXPRESS vol:16 issue:22 status: published

We present the design, fabrication, and testing results of a single chip (2 cm×4 cm) micro gas separation column (μGC) with an embedded non-cascaded micro thermal conductivity detector (μTCD). Our unique design coupled with RIE-Lag enabled 3D etching technology offers several advantages over previously reported designs including simple 2-mask fabrication and operation (no flow restrictors needed), capability for different flow velocities for the column and detector, low dead volume, low pressure drop, low detector power consumption, and an injection-event indicator. Our particular design is distinctly different from others in the number of fluidic ports (only 2 ports), channel design (circular cross section), and column type (open tubular). This μGG- μTCD chip separated and detected a 200 nl sample mixture consisting of alkanes in less than 2 minutes with power dissipation less than 400 mW.

Vertical integration of amorphous hydrogenated silicon diodes on CMOS readout chips offers several advantages compared to standard CMOS imagers in terms of sensitivity, dynamic range and dark current while at the same time introducing some undesired transient effects leading to image lag. Performance of such sensors is here reported and their transient behaviour is analysed and compared to the one of corresponding amorphous silicon test diodes deposited on glass. The measurements are further compared to simulations for a deeper investigation. The long time constant observed in dark or photocurrent decay is found to be rather independent of the density of defects present in the intrinsic layer of the amorphous silicon diode.

International audience; In this letter, we report the first experimental demonstration of micro-disk resonators that are vertically-coupled to their buried access waveguides on III-V semiconductor epitaxial structures using an original fabrication process. The here-proposed and validated three-dimensional integration scheme exploits selective lateral thermal oxidation of aluminium-rich AlGaAs layers. Compared to the previously reported processing techniques, this new scheme is simpler as it does not require any planarization or substrate transfer steps. As a proof-of-principle demonstration of this approach, 250 µm-diameter micro-disk devices exhibiting quality factor reaching ~8500 have been successfully fabricated.

A regrowth-free single-mode laser that is made using standard UV photolithography is reported. The laser achieves a single-mode side-mode suppression ratio of 37 dB, linewidth of 450 kHz, and tunes across 2.9 nm and is suitable for monolithic integration as a distributed feedback replacement, due to a large free spectral range of 60 nm.

Giant Magnetoresistance (GMR) based technology is nowadays the preferred option for low magnetic fields sensing in disciplines such as biotechnology or microelectronics. Their compatibility with standard CMOS processes is currently investigated as a key point for the development of novel applications, requiring compact electronic readout. In this paper, such compatibility has been experimentally studied with two particular non-dedicated CMOS standards: 0.35 μm from AMS (Austria MicroSystems) and 2.5 μm from CNM (Centre Nacional de Microelectrònica, Barcelona) as representative examples. GMR test devices have been designed and fabricated onto processed chips from both technologies. In order to evaluate so obtained devices, an extended characterization has been carried out including DC magnetic measurements and noise analysis. Moreover, a 2D-FEM (Finite Element Method) model, including the dependence of the GMR device resistance with the magnetic field, has been also developed and simulated. Its potential use as electric current sensors at the integrated circuit level has also been demonstrated. © 2014 Elsevier Ltd.

San Francisco, California, United States; International audience; Lattice-matched GaP-based nanostructures grown on silicon substrates is a highly rewarded route for coherent integration of photonics and high-efficiency photovoltaic devices onto silicon substrates. We report on the structural and optical properties of selected MBE-grown nanostructures on both GaP substrates and GaP/Si pseudo-substrates. As a first stumbling block, the GaP/Si interface growth has been optimised thanks to a complementary set of thorough structural analyses. Photoluminescence and time-resolved photoluminescence studies of self-assembled (In,Ga)As quantum dots grown on GaP substrate demonstrate a proximity of two different types of optical transitions interpreted as a competition between conduction band states in X and Γ valleys. Structural properties and optical studies of GaAsP(N)/GaP(N) quantum wells coherently grown on GaP substrates and GaP/Si pseudo substrates are reported. Our results are found to be suitable for light emission applications in the datacom segment. Then, possible routes are drawn for larger wavelengths applications, in order to address the chip-to-chip and within-a-chip optical interconnects and the optical telecom segments. Finally, results on GaAsPN/GaP heterostructures and diodes, suitable for PV applications are reported

We present the monolithic integration of deep-submicrometer complementary metal-oxide-semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance, and the solar cells on top show an efficiency of 8.4 ± 0.8% and a yield of 84%, both values being close to the glass reference. The main integration issues, i.e., adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress, can be resolved while maintaining standard photovoltaic processing. A tight process window is found for the manufacturing of CIGS solar cells on the CMOS side of the microchip. More process margin exists for backside integration.

A micro-bimorph cantilever is monolithically integrated with a photonic crystal micro-cavity based device, using surface micro-machining techniques. The integrated cantilever is equipped with self-aligned dielectric tips with respect to the holes of the photonic crystal and on electrostatic actuation, the tips move into the holes, providing electro-opto-mechanical modulation of guided waves. The device is designed to operate in the C-band of the telecommunication wavelengths and constitute a promising candidate for future integrated optical devices.

The monolithic integration of a detector stage comprising a photodiode and a field-effect transistor with a load resistor and a wavelength duplexer, realized in the GaInAsP/InP material system, is described. Design considerations, in particular for the wavelength duplexer, but for the complete chip as well, are reported, and details related to the realization of the device are given. Chips were mounted into housings and operated in a 1.3- mu m/1.55- mu m bidirectional transmission link. At 576 Mb/s and 10/sup -9/ bit error rate, the sensitivity of the module is -21 dBm, the intrinsic sensitivity of the receiver is -28 dBm, and the gain-bandwidth product for the lowest noise bias conditions is 3.8 GHz. >

Date of Conference: 7-9 December 2009 Conference Name: 2009 IEEE International Electron Devices Meeting, IEDM 2009 We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quality single crystal Ge selectively grown heteroepitaxially on Si using Multiple Hydrogen Anealing for Heteroepitaxy(MHAH) technique. Until now low source/drain series resistance in Ge n-MOSFETs has been a highly challenging problem. Source and drain are formed by implant-free, in-situ doping process for the purpose of very low series resistance and abrupt and shallow n+/p junctions. The novel n-MOSFETs show among the highest electron mobility reported on (100) Ge to-date. Furthermore, these devices provide an excellent Ion/Ioff ratio(4× 103) with very high Ion of 3.23μA/μm. These results show promise towards monolithic integration of Ge MOSFETs with Si CMOS VLSI platform.