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The performance of the material is demonstrated in a top gate, bottom contact device architecture operational in air without the requirement for device encapsulation. From a device performance aspect, we also highlight the influence that contact resistance has on the mobility. Keywords: Organic transistor, OFET, OTFT, soluble semiconductor, high mobility, crystalline semiconductor

The determination of trap state density is demonstrated using high frequency capacitance measurements on metal-oxide-polysilicon-silicon structures. An exact transmission line model is used to model equilibrium capacitance-voltage curves. Values of trap state density are compared with those obtained using more complicated structures.

High-frequency ring oscillators with sub-microsecond stage delay fabricated from spin-coated films of a specially formulated small-molecule/host-polymer blend are reported. Contacts and interconnects are patterned by photolithography with plasma etching used for creating vias and removing excess material to reduce parasitic effects. The characteristics of transistors with 4.6 I¼m channel length scale linearly with channel width over the range 60â��2160 I¼m. Model device parameters extracted using Silvaco's Universal Organic Thin Film Transistor (UOTFT) Model yield values of hole mobility increasing from 1.9 to 2.6 cm2 Vsâ��1 as gate voltage increased. Simulated and fabricated Vgs = 0 inverters predict that the technology is capable of fabricating 5-stage ring oscillators operating above 100 kHz. Initial designs operated mainly at frequencies in the range 250â��300 kHz, due to smaller parasitic gate overlap capacitances and higher supply voltages than assumed in the simulations. A design incorporating graded inverter sizes operates at frequencies above 400 kHz with the best reaching 529 kHz. The corresponding stage delay of 189 ns is the shortest reported to date for a solution-processed p-type semiconductor and compares favorably with similar circuits based on evaporated small molecules. Significant further improvements are identified which could lead to the fabrication of digital circuits that operate at much higher bit rates than previously reported.

The fabrication of high resolution light emitting polymer (LEP) OLED displays using ink jet printing to deposit the hole conducting and conjugated polymer electroluminescent components has required the development of both printing and ink technology. We review the issues associated with meeting the technology requirement and split these into the areas of ink delivery, getting the correct volume out of ink jet nozzles with well defined velocity and direction; surface energy considerations to maximize aperture ratio and display resolution; solution drying to form flat films and solution formulation to create polymer films that perform as well as films created by conventional spin coating. In addition we will describe the current status of the technology both in terms of polymer performance for both passive and active matrix applications, printing technology and polymer ink performance.

This note reports on the noise of CMOS devices. It is shown experimentally that a weak boron threshold implant (∼1012 cm−3) can influence the 1/f noise levels. For wafers with threshold adjustment the p-channel noise decreases whilst the n-channel noise increases. The changes in the n/p noise ratio with/without threshold implantation are predicted using a simple model in conjunction with carrier profile simulations.

We have developed a 14.1 inch full color polymer LED display, based on an a-Si TFT backplane, using ink jet printing, which does not show visible swathe marks during display operation. To remove the swathe marks, we have developed the single path printing technology for the hole-conduction layer deposition to significantly reduce the complexity of interlacing printing across the panel, which is known as an alternative to remove the swathe marks. In addition, we have adopted the interlayer process to increase the lifetime of ink jet printed displays. These technologies will enable the scale-up of the ink jet printed AMOLED applications to larger size displays, such as desktop monitors and TVs.

We have developed polymer LED displays using ink jet printing without visible swathe marks which can be observed during display operation. In addition, we have also developed a single-pass printing technology for hole-conduction layer deposition to significantly reduce the complexity of interlacing printing across the panel which is known as an alternative to remove the swathe mark.

The latest developments in light emitting polymer (LEP) technology at CDT continues to show steady progress. Device performance is described for blue, green and red systems as well as a high performance yellow system in terms of device efficiency and stability. Some of the issues associated with the commercialisation of LEP technology including the development, of direct patterning techniques enabling full colour passive and active matrix display will be presented.

For the first time, n-channel MOSFETs with elevated source and drain structures realised by selective epitaxial growth (SEG) of silicon using silane only have been stressed under various conditions. Depending on the gate voltage, up to 10 times improvement in hot-electron related degradation has been observed compared with the standard MOSFET structure. This has been attributed to the alleviation and spreading of the lateral electric Meld near the drain end of the transistor because of the very shallow and graded junctions obtained in elevated S/D structures.

The fabrication of an Sb delta-doped Si n-MESFET grown by molecular-beam epitaxy (MBE) and a low-energy Sb ion source is reported. The FETs have gate lengths of 2 mu m and showed a transconductance as high as 28 mS/mm and a gate breakdown voltage of 3.7-4.8 V.

Secco and periodic etches have been used to delineate n+p and p+n junctions found in ULSI CMOS. Preliminary trials indicated that delineated depth depends on etch time. An interpretation of these results in terms of etching of the substrate material leads to a simple expression between delineated depth and etch time. Once this relation has been established the technique allows a quick and consistent check on two dimensional dopant profiles and has been used on shallow junctions found in deep submicrometre structures.

Defects present in semiconductor layers can lead to increased transistor low frequency noise. This paper reports on the noise performance degradation caused by modern complementary metal-oxide-semiconductor (CMOS) and bipolar-CMOS (BiCMOS) processing techniques, these being the rapid thermal annealing (RTA) of metal-oxide-semiconductor field effect transistors (MOSFETs) and the use of polysilicon emitters in bipolar transistors. A rise in both the bulk and oxide defect densities was thought to be responsible for the increased noise of RTA MOSFETs over conventionally annealed devices. A significant low frequency noise component was discovered to be present in poly-silicon-emitter transistors. This was thought to be due to the presence of SiO2 at the polysilicon-single-crystal interface.

CMOS devices fabricated with a rapid thermal anneal source and drain activation have been compared with similar devices fabricated with a standard furnace anneal. Measurements have been made of low frequency noise, average interface state density, channel mobility, threshold voltage and bulk states using DLTS. Results show that in some instances RTA can have a deleterious effect on device performance that appears to be due to the rapid rates of cooling that can occur when using this techology.