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In this paper, a rigorous methodology for extracting the thermal compact model parameters of packaged chips is presented. The methodology is based on using a custom-designed test chip with multiple heating and temperature sensing elements in order to predict the temperature distribution in packaged chips after packaging. The technique involves measurement of various chips with different thicknesses, different packages, and for different power dissipation scenarios through which the thermal model parameters can be extracted. The results show that ultrathin chips with a total thickness below $20~\mu \text{m}$ experience a dramatically increased temperature for localized heat dissipation. In addition to this, the measurements conducted in time domain and frequency domain show that at high enough frequencies of heat pulsing, the temperature variations become independent of the thermal boundary conditions of the chip. The measurement results are compared to the finite-element method simulation data. The simulations together with the measurement methodology serve as a technique to extract the thermal compact model parameters of packaged chips after being fabricated and packaged in an accurate and efficient way.

This paper presents the design, fabrication and characterization of digital logic gates, flip-flops and shift registers based on low-voltage organic thin-film transistors (TFTs) on flexible plastic substrates. The organic transistors are based on the p-channel organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) and have channel lengths as short as 5 μ m and gate-to-contact overlaps of 20 μ m. The organic TFT is modeled which allows us to simulate different logic gate architectures prior to the fabrication process. In this study, the zero-VGS, biased-load and pseudo-CMOS logic families are investigated, where their static and dynamic operations are modeled and measured. The inverter and NAND gates use channel length of 5 μ m and operate with a supply voltage of 3 V. Static and dynamic master-slave flip-flops based on biased-load and pseudo-CMOS logic are designed, fabricated and characterized. A new design for biased-load dynamic flip-flops is proposed, where transmission gate switches are implemented using only p-channel transistors. 1-stage shift registers based on the new design and fabricated using TFTs with a channel length of 20 μ m operate with a maximum frequency of about 3 kHz.

Flexible electronics combined with new materials and fabrication processes offer unique characteristics such as mechanical flexibility, thin-form factor, large area scaling feasibility, and adaptability to irregular surfaces. In this work, a smart electronic skin adopting the hybrid system-in-foil concept is designed to monitor the uniaxial bending of a robotic gripper. The newly designed smart skin contains an array of printed strain gauges, organic thin-film transistor (TFT) addressing circuits and a 20 μm ultra-thin silicon readout chip, all integrated on the same polymeric foil. The silver-ink printed strain gauges achieve a relative resistance sensitivity ΔR/R of 2% and a gauge factor of 2. In addition, the organic TFT multiplexer containing a three-stage shift register and analogue switches operate at a frequency of 100 Hz and a supply voltage of 3 V. The ultra-thin silicon chip provides the functions of system control, strain gauge readout, analogue-to-digital conversion and serial communication.

Current electronic systems and circuits possess approximately 80 % of passive components. Thus, high performance integrated silicon-based passive components with high density are required to reduce the overall cost and bulkiness of the systems. This paper presents the development of high-density ultra-thin 3D capacitors in silicon, one of the important passive components exploited in approximately all the circuits for SiP, 3D-integration and flexible systems. The 3D structure is achieved by using deep reactive ion etching (DRIE) process. The substrate and the polysilicon act as the two electrode plates with silicon dioxide as the dielectric. Two designs with different pitches are investigated with successful back-grinding of the substrate to 50$\mu$ m thin and 22$\mu$ m ultra-thin singulated capacitors. Capacitive densities of 36.25 nF/mm 2 and 28.75 nF/mm 2 over a frequency bandwidth of 100 KHz are presented. The reduced thickness and flexible nature of these ultra-thin capacitors (

Hybrid System-in-Foil exploits the complementary benefits of integrating embedded silicon chips with on-foil passive and active electronic components. In this work, the design, fabrication and characterization of three on-foil components, namely a humidity sensor, near field communication antenna and organic thin-film transistors, are investigated.

This paper presents relative humidity sensors based on electrochemical and capacitive principles. The sensors are fabricated on flexible polymer substrates, which are used for ultra-thin chip embedding. The electrochemical sensor consists of spin-coated nanosheets, which shown huge range (about 5 orders of magnitude) and fast response (< 2 s). The sensor film thickness as well as ionic conductivity change upon moisture absorption. The measured sensor relative conductance change on the flexible substrate is 368%. In addition, a 3-pm thick conventional capacitive sensor is fabricated on the polymer substrate, together with a humidity-insensitive reference capacitor. The measured sensor relative sensitivity is about 75% with a response time of about 6 s. Finally, a sensor system-in-foil is demonstrated using discrete components of the ultra-thin capacitive sensor and a 30-pm thick capacitance-to-digital readout chip.

This paper presents analysis of the charge storage behavior in organic thin-film transistors (OTFTs) by means of admittance characterization, compact modeling, and 2-D device simulation. The measurements are performed for frequencies ranging from 100 Hz to 1 MHz and bias potentials from zero to -3 V on top-contact OTFTs that employ air-stable and high-mobility dinaphtho-thieno-thiophene as the organic semiconductor. It is demonstrated that the dependence of the intrinsic OTFT gate-source and gate-drain capacitances on the applied voltages agrees very well with Meyer's capacitance model. Furthermore, the impact of parasitic elements, including fringe current and contact impedance, is investigated. The parameters used for the simulation and modeling of all the dynamic characteristics correspond closely to those extracted from static measurements. Finally, the implications of the admittance measurements are also discussed relating to the OTFTs dynamic performance, particularly the cutoff frequency and the charge response time.

Bottom-gate, top-contact (inverted staggered) organic thin-film transistors with a channel length of 1 μm have been fabricated on flexible plastic substrates using the vacuum-deposited small-molecule semiconductor 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C10-DNTT). The transistors have an effective field-effect mobility of 1.2 cm2/V s, an on/off ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 ns per stage at a supply voltage of 3 V. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V.

This paper presents S-parameter characterization and a corresponding physics-based small-signal equivalent circuit for organic thin-film transistors (OTFTs). Furthermore, the impact of misalignment between the source/drain contacts and the patterned gate on the dynamic TFT performance is explored and a simple method to estimate the misalignment from the measured S-parameters is proposed. An excellent fit between theoretical and experimental S-parameters is demonstrated. For this study, OTFTs based on the air-stable organic semiconductor dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) having a channel length of 1 μm and a gate-to-contact overlap of 5 or 20 μm and being operated at a supply voltage of 3 V are utilized. The intentional asymmetry between gate-to-source and gate-to-drain overlaps is precisely controlled by the use of high-resolution silicon stencil masks.

A 3.3 V 6-bit binary-weighted current-steering digital-to-converter converter (DAC) using low-voltage organic p-type thin-film transistors (OTFTs) is presented. The converter marks records in speed and compactness owing to an OTFT fabrication process that is based on high-resolution silicon stencil masks. The chip has been fabricated on a glass substrate and consumes an area of 2.6× 4.6 mm2. The converter has a maximum update rate of 100 kS/s and a maximum output voltage swing of 2 V. The measured DNL and INL at an update rate of 1 kS/s are - 0.69 and 1.16 LSB, respectively. A spurious-free dynamic range (SFDR) of 32 dB has been measured for output sinusoids at 31 Hz (update rate of 1 kS/s) and 3.1 kHz (update rate of 100 kS/s).

This paper presents a novel implementation of variable uniaxial mechanical stress model to be used with DC circuit simulation, e.g. using BSIM3v3 transistor model. Based on transistor measurements under various uniaxial stress conditions two stress-dependent parameters are identified, namely the carriers mobility and to a lesser extend the carrier saturation velocity. The effect of the parasitic source/drain resistance on the piezoresistive coefficient determination is addressed in detail. Using the fundamental piezoresistive coefficients, the model has implemented a general relation to calculate the coefficients for arbitrary directions of current and stress in the (0 0 1) silicon (Si) plane. The extended transistor model allows for simulating the effect of uniaxial stress on any MOSFET geometry, under different operation conditions and for any combination of the drain current and stress orientations in the (0 0 1) silicon (Si) plane. The method proposed in this paper is validated by static and dynamic stress-dependent simulations and comparison with experimental data. The method is simulator-independent and can be adapted to other bulk CMOS technologies including SOI processes.

System-in-Foil (SiF) is an emerging field of large-area polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (E-Ink) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin (

A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.

This letter presents the first comprehensive experimental studies on the frequency response of staggered low-voltage organic thin-film transistors (OTFTs) using S-parameter measurements. The transistors utilize air-stable dinaphtho-thieno-thiophene as the organic semiconductor with various channel lengths and gate overlaps. A peak cutoff frequency of 3.7 MHz for a channel length of 0.6 μm, gate overlap of 5 μm, and a supply voltage of 3 V is achieved. In view of the low supply voltage and air-stability, this result marks a record achievement in OTFT technology. The channel length dependence of the cutoff frequency is described in a compact model and a close correspondence to the measured data of OTFTs with variable device dimensions is shown. Moreover, the cutoff frequencies at different gate biases are found to be proportional to the dc transconductance.

Manufacturing ultra-thin chip is an emerging field in semiconductor technology that is driven by 3-D integrated circuits and flexible electronics. Unlike bulk silicon (Si) chips with thickness greater than 400 μm, the thermal management of ultra-thin Si chips with thickness smaller than 20 μm is challenging due to the increased lateral thermal resistance implying stringent cooling requirements. Therefore, a reasonable prediction of temperature gradients in such chips is necessary. In this work, a thermal chip is implemented in an ultra-thin 0.5 μm CMOS technology to be employed in surface steady-state and transient temperature measurement. Test chips are either packaged in a Pin Grid Array (PGA) ceramic package or attached to a flexible polyimide substrate. The experimental results show an on-chip temperature gradient of ∼15 °C for a dissipated power of 0.4 W in the case of the PGA package and ∼30 °C for the polyimide substrate. The time constants are ∼50 s and ∼1 s for the PGA and the polyimide packages respectively. The measurements are complemented by FEM simulations using ANSYS 14.5 workbench and spice simulations using an equivalent lumped-component thermal circuit model. The lumped-element thermal circuit model is then used for the surface temperature prediction, which is compared to measurement results.

This paper presents a CMOS stress sensor for uniaxial, in-plane flex measurement. The sensor is to be fabricated as an ultra-thin chip in order to adapt to surface shape. The sensor generates 2×10-bit data from piezo-resistive elements, via on chip stress insensitive readout circuitry. Unlike the directional selectivity of the strain gauges, the uniaxial in-plane stress vector can be measured in any direction by this sensor. In addition, the MOSFET stress macro model used for the sensor flex simulations is presented. It is used for the sensor flex simulations. It supports DC, AC, and transient analysis with any analog simulator.

Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates. Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents, which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate. By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.

System-in-foil (SiF) technology calls for low cost, ultra-thin and, high-performance high-voltage transistors to satisfy the need for high-voltage driving capability in many of the emerging flexible display technologies. An ultra-thin (20 μm) N-type lateral DMOS transistor (N-LDMOS) in Chipfilm™ technology, developed for this application, is presented. The fabrication process is fully compatible with conventional high-voltage CMOS technology using shallow trench isolation (STI). The N-LDMOS has a breakdown voltage >100 volts with a maximum drain current of 4.4 mA at a channel length of 9 μm and a width of 50 μm. At drain voltage V ds = 100 V, self-heating causes a reduction in drain current up to 19% on a silicon carrier wafer and 35% on polyimide (PI) foil relative to the drain current without self heating, thus indicating power dissipation to be one of most serious issues in flexible electronics.

For ultra-thin chips (

Mechanical deformation changes the silicon material’s electrical resistivity (Smith, Phys Rev 94(1):42–49, 1954). This is an important property of the material. The effect known as ‘piezoresistive’ has found many applications over time. In micro-electro-mechanical systems (MEMS), for example, it has enabled the integration of pressure sensors with complementary metal-oxide semiconductor (CMOS) circuits that translate the stress into voltage signals. The piezoresistive effect has been also observed and studied in the metal-oxide-silicon field effect transistor (MOSFET), the principal component of a CMOS integrated circuit (IC). In transistors the strain affects the mobility of the carriers and as a result the drain current and the speed of the transistor. Although scaling tends to achieve its limitations, the need to further increase the MOSFET performance by having more power and speed remains. Based on mobility enhancement due to the stress/strain applied to the MOSFET channel, the ‘strained Si’ technique has been chosen as a new degree of freedom to further improve MOSFET performance and to defeat scaling limitations. In this chapter we discuss aspects related to the piezoresistive effect in bulk Si and its modifications in MOSFET Si inversion layer. We analyse the strain effects on Si electronic band structure and its transport properties. Piezoresistive coefficient values from literature for bulk Si and MOSFETs under uniaxial strain are presented and compared.

Apparently anomalous and transient piezoresistive effects are observed from CMOS transistors and diffused resistors fabricated on 20 µm thin, flexible chips for system-in-foil (SiF) applications. We show that this effect results from a transformation of uniaxial to biaxial stress according to the Poisson ratio of the visco-elastic epoxy glue used for chip attachment. This effect is further analyzed through current mirror circuits composed of orthogonally oriented transistors.

Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips on foil will not only provide solutions whenever high circuit performance and/or complexity are required but also in a heterogeneous integration with organic or TFT electronic components on foil, such as for flexible displays. Thinning of conventional CMOS chips in post-processing tends to be unreliable and costly due to difficulties in the control of the grinding process applied to fully processed CMOS wafers or the need of employing expensive silicon-on-insulator (SOI) and handle substrates.

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness ⩽20 μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the builtin devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.