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Poly-connected MOSFETs can reduce chip area due to replacing some metal layer routing. Compared with conventional MOS, resistance of connecting poly (P2) is an additional factor which impacts MOS electrical performance, besides LDD and source/drain parasitic resistance. Conventional parasitic resistance extraction method requires a series of different gate length test structures. A new extraction method of parasitic resistance is demonstrated here, that is to extract the parasitic resistance from forward biased current vs. voltage characteristics of drain/bulk junction diode based on a single MOS test structure. Using this method, P2 layer deposition loading effect is successfully detected and poly space effect (PSE) of poly-connected MOSFETs can be well modelled in SPICE model. This new extraction method can also be applicable for conventional MOSFETs.

Device with shallow trench isolation (STI) has inverse narrow width effect (INWE), that is the threshold voltage of narrow width transistors is lower than that of large width transistors. The conventional methods of improving INWE focus on STI module optimization, such as active area corner rounding, step height and divot control. In this paper, a new approach by implant optimization is proposed to improve INWE. For low power PMOS device, phosphorus halo implant is often used for its lower diode leakage characteristics. This paper reports optimized dual halo implant approach with both arsenic and phosphorus implants to improve INWE. This approach gives larger Gm*Rout and lower digital product chip stand-by current without reliability degradation.

A physics-based new gated diode SPICE compact model is provided considering the following two effects: (1) the leakage current under reverse bias of gated diode caused by the gate/diffusion overlap tunneling current; (2) the substrate conductivity modulation associated with high injection of carriers due to mobility saturation during high current transmission line pulse (TLP). The new SPICE model matches the silicon data under both ESD TLP and normal DC forward/reverse bias very well. The model is scalable in terms of finger width and number.

The morphology of the top surface for HVPE GaN layers grown on a MOCVD GaN template with a thin LT-AlN interlayer was investigated. This surface is characterized by the formation of numerous hillocks associated with screw dislocations or nanopipes. Their size is large and may reach more than 1 mm. The rocking curves of the 002 and 102 reflections correspond to a relaxed layer. The HREM images of the as-deposited and annealed interlayers show a perfect atomic structure with a very abrupt AlN/HVPE GaN interface. Thus, the deposition of the LT-AlN layer has promoted the growth of an HVPE layer with an excellent crystalline quality.

In this paper, technology computer aided design (TCAD) was applied to optimize the fabrication process to reduce the parasitic capacitance of PMOS transistor at the source/drian (S/D) junction (Cj) in developing the 65 nm low leakage (65 nmLL) technology. It was found that Cj can be effectively reduced by combining relative high-energy well implant and proper threshold voltage (Vt) implant method. Through measured data and TCAD simulation, this paper also demonstrates a ?doping compensation effect? by tuning Vt and Halo implants with proper species, energy, and dosage, to achieve the Cj reduction.

High-quality GaN films were deposited by hydride vapor phase epitaxy (HVPE) on metalorganic chemical vapor deposition GaN templates using an anodized aluminum oxide mask. High-resolution X-ray diffraction, scanning electron microscopy, and cathod-oluminescence were used to highlight the excellent crystalline quality of the films, and the optical properties at different positions of the as-grown layers. The optical properties of the GaN films improved with increased film thickness. The PL peak position indicates stress relaxation by the AAO mask.