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The formation of a copper silicide interfacial layer by surface reaction in a plasma enhanced chemical vapour deposition (PECVD) system has been studied. Tri-methyl silane (TMS, SiH(CH"3)"3) has been employed as the Si source as an alternative to more conventional silane (SiH"4) approach. TMS precursor has been chosen due to improved control of Si penetration into the copper [S. Chhun, L.G. Gosset, N. Casanova, J.F. Guillaumond, P. Dumont-Girard, X. Fedespiel, R. Pantel, V. Arnal, L. Arnaud, J. Torres, Microelectronic Engineering 76 (2004) 106-112]. AFM, SIMS, light scattering, FT-IR spectroscopy and dielectric constant measurements were performed on various stacks to evaluate CuSiN formation. Resistance, leakage, and electromigration (EM) reliability characterization were performed on test structures based on 65nm design rules. Nitridation step in silicidation process was shown to have positive impact on EM reliability, minimizing the line resistance increase.

The FSG (fluorine-doped silicon glass) was introduced as dielectric for copper interconnects in order to take advantage of its lower dielectric constant. With a gain of 18% in the constant value, it makes the shrink of metal dimension possible for 0.12- µm technology devices with limited cross-talks or delays in the information transmission. In spite of its strong sensitivity to water and moisture absorption, we could integrate this material in the dual damascene structure for copper application for 0.12- µm technology. The use of appropriate capping layer and optimisation of fluorine content made the integration possible with optimal dielectric properties.

The increasing use of closely spaced narrow interconnections and generally reduced feature sizes in modern IC technology has led to a requirement for anisotropic etching of high performance metallizations. Etching processes addressing this requirement should exhibit good uniformity and reproducibility, a good selectivity over underlying materials and the mask to ensure a good pattern fidelity. WGe based barriers have good prospects in sub-micron contact barrier technology. The purpose of the present paper is to investigate the reactive ion etching (RIE) of blanket deposited AlCu/WGe/sub x//Ti films on SiO/sub 2/ in a chlorine based plasma chemistry employing a Cl/sub 2/, SiCl/sub 4/, He mixture. Various aspects of the metal stack etching including profile control, etch rate and selectivity to oxide are discussed in detail.

This paper compares three different schemes to pattern dual damascene (DD) structures. The Self Aligned (SA), Via First (VF), and Trench First (TF) architectures are compared in terms of complexity, process latitude, and sensitivity to lithography misalignment using 0.18-/spl mu/m copper/oxide two metal level structures. The integration of thick metal lines is also discussed, for the upper levels of interconnects. This study shows that the VF architecture has the best via chain yield, regardless of the test configuration, and allows to pattern thick metal DD structures with high yield. The VF technique was used to manufacture a six copper level device, with functional yield similar to that obtained with an AlCu/HSQ Back End Of Line (BEOL).