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Many applications show tolerance to inaccuracies. These can be exploited to build faster circuits with smaller area and lower power. This is particularly true for the hardware accelerators in heterogeneous computing systems. A major problem with approximate computing is that the resulting approximated circuit is highly dependent on the training data. Previous works often rely on static training results. If the workload is dynamic in nature or changes over time, output errors may reach unacceptable levels. Therefore, dynamic control methods are needed to solve this problem. To address this issue, in this paper, we propose an approximate self-adaptive architecture that autotunes itself at runtime based on the workload. Two different control mechanisms are proposed, one based on a regular heartbeat (HB), which resets the approximate circuits at regular intervals and the other based on internal lightweight checkers (LWCs). These checkers detect a change in the workload and reset the approximations. Experimental results show that our proposed methods work well leading to very good results compared to other approximation methods while keeping the output error within the given maximum error threshold at relatively low-area overheads, on average 8% and 8.5% for HB and LWC method, respectively, and delay overheads 5.9% and 8.1%. [ABSTRACT FROM AUTHOR]

Many classes of applications exhibit significant tolerance to inaccuracies in their computations. Some examples include image processing, multimedia applications, and machine learning. These inaccuracies can be exploited to build circuits with smaller area, lower power, and higher performance. Most previous work restricts the approximate optimizations to a particular level of abstraction or step within the VLSI process. This paper shows that a combined multilevel approach is far more superior. Thus, this paper exploits different optimizations visible only at each particular level, leading to better results than single-level methods. Moreover, approximate computing is highly data-dependent. Therefore, in this paper, we study the stability of the approximate circuits when the circuit is optimized for a particular data distribution and the final workload differs from it. Previous work mainly considers a single input data distribution and that this distribution is equal to the final workload. Results show that our proposed method can find better and more optimal configurations compared with previous work and can achieve circuits, which are more robust in environments with dynamic workloads. [ABSTRACT FROM AUTHOR]

One of the biggest advantages of C-Based VLSI design over traditional RT-level design is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. So far previous works have focuses on either pruning the design space or by creating predictive models in combination with different metaheuristics. In this letter, we present a hierarchical method which makes use of modern HLS tool’s options to synthesize functions as functional operators in order to explore these separately. Our method therefore explores each function separately and then performs a merging stage in order to obtain the overall dominating results. Moreover our proposed method detects if any changes in the behavioral description have happened between two exploration executions and only explores those functions which have been affected by the source code changes, while the results of the previous exploration are reused, thus enabling for incremental DSE. Results show that our method is very efficient. [ABSTRACT FROM PUBLISHER]

High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness. [ABSTRACT FROM PUBLISHER]