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A 39.8–44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 pspp ISI and 0.2 psrms RJ at 0.87 W. The RX achieves a jitter tolerance of 0.6 UIpp at 100 MHz and an input sensitivity of 20 mVpp\mathchar"702D diff at 1.05 W. The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 2^31 -1 PRBS at BER< 10 ^-12 over a channel with > 21 dB loss at Nyquist frequency. [ABSTRACT FROM PUBLISHER]

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 psrms RJ, 0.8 pspp DJ, and a \pm \0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20–27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7-mV ppd input sensitivity and a 0.7-UIpp high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively. [ABSTRACT FROM AUTHOR]