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The feasibility of a 3-D-NAND-Flash-based heavy-ion detector is explored. The possibility of measuring the angle of incidence and the linear energy transfer (LET) of impinging particles by studying the pattern of the threshold voltage shifts along the track of the affected cells is discussed. The results of the experiments with different beams (both directly and indirectly ionizing) are illustrated. A set of Monte Carlo simulations is also presented, to study sensitive volumes on 3-D NAND floating gate cells and explore the possibility of distinguishing the effects generated by ionizing particles with different features, such as LET and angle of incidence.

The effects of total ionizing dose on 3-D flash memories irradiated with gamma rays are investigated. The evolution and shape of threshold voltage distributions are studied versus dose for floating gate cell NAND arrays with vertical-channel architecture. The dependence of total dose effects on the logic level stored in the cells, the underlying mechanisms, and the raw bit errors induced by gamma-rays are discussed. The results are then compared with planar NAND and NOR flash technologies, in terms of threshold voltage shifts and bit error rates, showing improvements over previous generations due to the new cell structure.

The effects of total ionizing dose on 3-D NAND floating gate cells with vertical architecture are analyzed as a function of the cell depth in the pillar. The focus of this work is on TID-induced threshold voltage shifts, but the implications on the raw bit error rates are also discussed. Underlying mechanisms are elucidated, concluding that due to the manufacturing process and the geometry of the pillars, the effects of total dose are larger at the bottom than at the top of the cell array.

A heavy-ion beam monitor based on 3-D NAND flash memories was designed and tested with heavy ions at high energy and low linear energy transfer (LET). The capability of measuring fluence, angle, uniformity, and LET of impinging particles is discussed, together with the advantages over SRAM-based implementations. We propose ad hoc algorithms for the extraction of the beam parameters, based only on user-mode commands. A validation of the system using low-LET ionizing particles impinging at different angles is presented. Experimental results show very good efficiency and accuracy.

The effects of heavy-ion irradiation on 3-D NAND flash memory cells are investigated. Threshold voltage distributions are studied before and after exposure, as a function of the linear energy transfer, fluence, and irradiation angle. Shifts are smaller in 3-D devices than those in planar ones, for the same equivalent bit density. The cell circular shape and the fact that the tunnel oxide and interpoly dielectric blocking layers are perpendicular to the semiconductor substrate make it possible to gain insight into the underlying upset mechanism, which cannot be obtained with planar devices. Evidence that energy deposition in the blocking oxide layer can contribute to charge loss from the floating gate is presented.

The sensitivity of vertical-channel 3-D NAND flash memories to wide-energy spectrum neutrons was investigated. The effects of neutron exposure on a 3-D floating gate (FG) cells were studied in terms of threshold voltage shifts and raw bit error rates. The neutron failure rates obtained in the accelerated tests were extrapolated to field conditions at sea level and aircraft altitudes. The results are compared with previous data on 3-D nand flash devices irradiated with heavy ions, as well as data on planar FG cell technologies.

We studied the angular dependence of heavy-ion induced errors and threshold voltage shifts in Flash memories. Combining experiments and Geant4-based simulations, we provide new insight about the sensitive volume in floating gate cells. At high LET, the sensitive volume for cells belonging to the heavy-ion induced secondary peak corresponds to a large part of the floating gate. The sensitive volume for upsets may be larger or smaller, depending on the relative position of the secondary peak with respect to the relevant reference voltage.

Heavy-ion irradiation of NAND flash memories under operating conditions leads to errors with complex, data-dependent signatures. We present upsets due to hits in the floating gate array and in the peripheral circuitry, discussing their peculiarities in terms of pattern dependence and annealing. We also illustrate single event functional interruptions, which lead to errors during erase and program operations. To account for all the phenomena we observe during and after irradiation, we propose an ldquoeffective cross section,rdquo which takes into account the array and peripheral circuitry contributions to the SEU sensitivity, as well as the operating conditions.

Heavy ions typical of the space environment have energies which exceed by orders of magnitude those available at particle accelerators. In this paper we are irradiating state of the art floating gate memories by using both a medium energy (SIRAD) and a high energy (RADEF) facilities. The corruption of stored information decreases when increasing ion energy. The proposed model deals with the broader track found for higher energy ions. Implications for testing procedures and for reliability considerations are discussed.

We irradiated floating gate (FG) memories with nor and nand architecture by using different TID sources, including 2 MeV, 98 MeV, and 105 MeV protons, X-rays, and Upsi-rays. Two classes of phenomena are responsible for charge loss from programmed FGs: the first is charge generation, recombination, and transport in the dielectrics, while the second is the emission of electrons above the oxide band. Charge loss from programmed FGs irradiated with protons of different energy closely tracks results from Upsi-rays, whereas the use of X-rays results in dose enhancement effects.

We are showing for the first time the charge loss due to heavy ion irradiation on Flash memory arrays organized following the NAND architecture. Results complement those previously found for devices featuring a NOR architecture: large charge loss can be expected after the hit of a single ion on a single memory cell. The resulting threshold voltage shift DeltaVTH grows with ion LET and with applied electric field across the tunnel oxide (that is, with the programming conditions) and cannot be explained by simple generation-recombination-transport models. Further, in Floating Gates hit by a single ion a percolation path develops across the tunnel oxide, able to slowly discharge the Floating Gate

We present the first evidence of single event upsets in 45-nm phase change memories caused by high linear energy transfer (LET) heavy ions at tilted angles along the word line. An- gular and LET dependences are presented, together with a discus- sion of the possible underlying mechanisms. The occurrence of a thermal spike, due to the ion passage, close to the heater/storage element interface is identified as the most plausible explanation. The upset cross section is compared with that of NOR Flash and finally the impact of scaling on the sensitivity of future memories is analyzed.

Flash memories operating in space are subject at the same time to the progressive accumulation of total ionizing dose and to intrinsic aging phenomena. In this work we investigate latent Total Ionizing Dose (TID) effects in 41-nm NAND single level cells that do not display neither floating gate errors nor any apparent kind of degradation after exposure. Retention of irradiated cells is analyzed at room and high temperature as a function of total dose previously received. We found that FG cell retention at room temperature is practically unchanged after a total dose up to 30 krad(Si). On the contrary, TID exposure slightly worsens the cell retention time during high-temperature tests. We attribute this behavior to the removal of compensating electrons from the tunnel oxide at high temperature.

We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of rough bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes.

We discuss new experimental results on the post-radiation annealing of Floating Gate errors in Flash memories with both NAND and NOR architecture. We investigate the dependence of annealing on the program level, linking the reduction in the number of Floating Gate errors to the evolution of the threshold voltage of each single cell. To understand the underlying physics we also discuss how temperature affects the number of Floating Gate errors.

NAND Flash memories are the leader among high capacity non-volatile memory technologies and are becoming attractive also for radiation harsh environments, such as space. For these applications, a careful assessment of their sensitivity to radiation is needed. In this contribution, we analyze TID effects on the many different building blocks of NAND Flash memories, including the charge pumps, row-decoder, and floating gate array. Since each of these elements have dedicated circuital and technological characteristics, we identify and study the characteristic failure mode for each part.