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In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length (${L}_{\mathrm {ch}}$) and channel thickness (${T}_{\mathrm {ch}}$) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in $256\times 256$ size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

In this paper, we show that parasitic elements have a significant effect on the dynamics of memristor circuits. We first show that certain -terminal elements such as memristors, memcapacitors, and meminductors can be used as nonvolatile memories, if the principle of conservation of state variables hold by open-circuiting, or short-circuiting, their terminals. We also show that a passive memristor with a strictly-increasing constitutive relation will eventually lose its stored flux when we switch off the power if there is a parasitic capacitance across the memristor. Similarly, a memcapacitor (resp., meminductor) with a positive memcapacitance (resp., meminductance) will eventually lose their stored physical states when we switch off the power, if it is connected to a parasitic resistance. We then show that the discontinuous jump that circuit engineers assumed to occur at impasse points of memristor circuits contradicts the principles of conservation of charge and flux at the time of the discontinuous jump. A parasitic element can be used to break an impasse point, resulting in the emergence of a continuous oscillation in the circuit. We also define a distance, a diameter, and a dimension, for each circuit element in order to measure the complexity order of the parasitic elements. They can be used to find higher-order parasitic elements which can break impasse points. Furthermore, we derived a memristor-based Chua's circuit from a three-element circuit containing a memristor by connecting two parasitic memcapacitances to break the impasse points. We finally show that a higher-order parasitic element can be used for breaking the impasse points on two-dimensional and three-dimensional constrained spaces. [ABSTRACT FROM AUTHOR]

The energy consumption during the operation of organic nonvolatile memory devices fabricated on a flexible polyethylene naphthalate (PEN) substrate is investigated. For bistable resistive memory devices, the applied external voltage and time are essential factors for switching the memory cell from the OFF to ON state because the amounts of voltage and time determine the applied energy needed to set the memory cell. Using the composite material polyimide (PI) and [6,6]‐phenyl‐C61 butyric acid methyl ester (PCBM) as the active layer of the bistable resistive memory devices on a flexible PEN substrate, nonvolatile unipolar switching behavior and good electrical reliability of PI:PCBM memory devices are observed, and the relationship between the applied energy and the switching characteristics for various applied voltages and times is characterized. The results of the performed experiments show that higher ON state currents are reached as greater set voltages or times are applied, and reliable switching behavior is observed at over ≈10−6 J of applied energy with at least 4 V of applied voltage and 10 ms of pulse time. [ABSTRACT FROM AUTHOR]