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The effects of total ionizing dose on 3-D NAND floating gate cells with vertical architecture are analyzed as a function of the cell depth in the pillar. The focus of this work is on TID-induced threshold voltage shifts, but the implications on the raw bit error rates are also discussed. Underlying mechanisms are elucidated, concluding that due to the manufacturing process and the geometry of the pillars, the effects of total dose are larger at the bottom than at the top of the cell array. [ABSTRACT FROM AUTHOR]

Floating gate cells in advanced NAND Flash memories, with single-level and multi-level cell architecture, were exposed to low-energy proton beams. The first experimental evidence of single event upsets by proton direct ionization in floating gate cells is reported. The dependence of the error rate versus proton energy is analyzed in a wide energy range. Proton direct ionization events are studied and energy loss in the overlayers is discussed. The threshold LET for floating gate errors in multi-level and single-level cell devices is modeled and technology scaling trends are analyzed, also discussing the impact of the particle track size. [ABSTRACT FROM PUBLISHER]