Search

The VIPIC1 readout integrated circuit was designed for X-ray Photon Correlation Spectroscopy experiments that are typically performed using mono-energetic (8 keV) X-rays at a synchrotron radiation facility. The device is a pixel detector with sparsification and parallel readout from the groups, yielding high timing resolution. Recent improvements in bonding alignment of wafers resulted in deliveries of 3D bonded wafers. The stacks, bonded with both the Cu-Cu thermo-compression method and the Cu DBI bonding method, yielded operational devices that have been tested. Chips (with a pixel pitch of 80~\mu\m) were also bonded to silicon pixelated sensors (with a pixel pitch of 100~\mu\m) and the assemblies were exposed to X-ray sources for the first time. The paper focuses on the test results, including the calibrated noise (ENC) and the conversion gain. The noise measured corresponded to 39~\e^ - and 70~\e^ - , respectively for the readout channels that were not connected and connected to the sensor diodes. The conversion gain varied from 43 to 52~\mu\V/e^ - as a function of the bias current in the front-end block. Essentially all the pixels on a small prototype were operational. [ABSTRACT FROM PUBLISHER]

A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 \muV/e^- to 50 \muV/e^- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e^- for a peaking time Tp=115\ ns and Cdet=1.2\ pF. With a DC-coupled CdTe detector, the ENC is 210 e^-\ rms for a peaking time Tp=380\ ns and Cdet=2\ pF and the leakage current Idleak=0.15\ nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e^-\ rms (at one sigma level). The ASIC is designed in a CMOS 0.35 \mum technology and its total area is 4800\times 5000\ \mum^2. [ABSTRACT FROM AUTHOR]