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Among other new device concepts, nickel silicide (NiSix)-based Schottky barrier nanowire transistors are projected to supplement down-scaling of the complementary metal-oxide-semiconductor (CMOS) technology as its physical limits are reached. Control over the NiSix phase and its intrusions into the nanowire are essential for superior performance and down-scaling of these devices. Several works have shown control over the phase, but control over the intrusion lengths has remained a challenge. To overcome this, we report a novel millisecond-range flash-lamp-annealing (FLA)-based silicidation process. Nanowires are fabricated on silicon-on-insulator substrates using a top-down approach. Subsequently, Ni silicidation experiments are carried out using FLA. It is demonstrated that this silicidation process gives unprecedented control over the silicide intrusions. Scanning electron microscopy and high-resolution transmission electron microscopy are performed for structural characterization of the silicide. FLA temperatures are estimated with the help of simulations.

Here, we report the observation of negative photoconductance (NPC) effect in highly arsenic-doped germanium nanowires (Ge NWs) for the infrared light. NPC was studied by light-assisted Kelvin probe force microscopy, which shows the depletion of carriers in n-Ge NWs in the presence of infrared light. The trapping of photocarriers leads to high recombination of carriers in the presence of light, which is dominant in the n-type devices. Furthermore, a carrier trapping model was used to investigate the trapping and detrapping phenomena and it was observed that the NPC in n-Ge occurred, because of the fast trapping of mobile charge carriers by interfacial states. The performance of n-type devices was compared with p-type NW detectors, which shows the conventional positive photoconductive behavior with high gain of 104. The observed results can be used to study the application of Ge NWs for various optoelectronic applications involving light tunable memory device applications.

This paper describes molecular layer doping of Ge nanowires. Molecules containing dopant atoms are chemically bound to a germanium surface. Subsequent annealing enables the dopant atoms from the surface bound molecules to diffuse into the underlying substrate. Electrical and material characterization was carried out, including an assessment of the Ge surface, carrier concentrations and crystal quality. Significantly, the intrinsic resistance of Ge nanowires with widths down to 30 nm, doped using MLD, was found to decrease by several orders of magnitude.

This article presents a review of various methods for extracting the key parameters of junctionless (JL) MOSFETs, namely, the threshold voltage, flat-band voltage, doping concentration, carrier mobility, and parasitic series resistance. The applicability and limitations of different methods are analyzed using numerical simulations and experimental data for planar and tri-gate nanowire JL transistors with various nanowire widths.

The transport properties of novel device architectures depend strongly on the morphology and the quality of the interface between contact and channel materials. In silicon nanowires with nickel silicide contacts, NiSi 2–Si interfaces are particularly important as NiSi 2 is often found as the phase adjacent to the silicide–silicon interface during and after the silicidation. The interface orientation of these NiSi 2–Si interfaces as well as the ability to create abrupt and flat interfaces, ultimately with atomic sharpness, is essential for the properties of diverse emerging device concepts. We present a combined experimental and theoretical study on NiSi 2–Si interfaces. Interfaces in silicon nanowires were fabricated using silicidation and characterized by high-resolution (scanning) transmission electron microscopy. It is found that {111} interfaces occur in ⟨110⟩ nanowires. A tilted interface and an arrow-shaped interface are observed, which depends on the nanowire diameter. We have further modeled NiSi 2–Si interfaces by density functional theory. Different crystallographic orientations and interface variations, e.g., due to interface reconstruction, are compared with respect to interface energy densities. The {111} interface is energetically most favorable, which explains the experimental observations. Possible ways to control the interface type are discussed.

This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 10(20) atoms cm(-3). Characterization of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials.

'Directing' block copolymer (BCP) patterns is a possible option for future semiconductor device patterning, but pattern transfer of BCP masks is somewhat hindered by the inherently low etch contrast between blocks. Here, we demonstrate a 'fab' friendly methodology for forming well-registered and aligned silicon (Si) nanofins following pattern transfer of robust metal oxide nanowire masks through the directed self-assembly (DSA) of BCPs. A cylindrical forming poly(styrene)-block-poly(4-vinyl-pyridine) (PS-b-P4VP) BCP was employed producing 'fingerprint' line patterns over macroscopic areas following solvent vapor annealing treatment. The directed assembly of PS-b-P4VP line patterns was enabled by electron-beam lithographically defined hydrogen silsequioxane (HSQ) gratings. We developed metal oxide nanowire features using PS-b-P4VP structures which facilitated high quality pattern transfer to the underlying Si substrate. This work highlights the precision at which long range ordered [similar]10 nm Si nanofin features with 32 nm pitch can be defined using a cylindrical BCP system for nanolithography application. The results show promise for future nanocircuitry fabrication to access sub-16 nm critical dimensions using cylindrical systems as surface interfaces are easier to tailor than lamellar systems. Additionally, the work helps to demonstrate the extension of these methods to a 'high [small chi]' BCP beyond the size limitations of the more well-studied PS-b-poly(methyl methylacrylate) (PS-b-PMMA) system.

To maintain semiconductor device scaling, in recent years industry has been forced to move from planar to non-planar device architectures. This alone has created the need to develop a radically new, non-destructive method for doping. Doping alters the electrical properties of a semiconductor, related to the access resistance. Low access resistance is necessary for high performance technology and reduced power consumption. In this work the authors reduced access resistance in top–down patterned Ge nanowires and Ge substrates by a non-destructive dopant in-diffusion process. Furthermore, an innovative electrical characterisation methodology is developed for nanowire and fin-based test structures to extract important parameters that are related to access resistance such as nanowire resistivity, sheet resistance, and active doping levels. Phosphine or arsine was flowed in a Metalorganic Vapour Phase Epitaxy reactor over heated Ge samples in the range of 650–700 °C. Dopants were incorporated and activated in this single step. No Ge growth accompanied this process. Active doping levels were determined by electrochemical capacitance–voltage free carrier profiling to be in the range of 1019 cm−3. The nanowires were patterned in an array of widths from 20–1000 nm. Cross-sectional Transmission Electron Microscopy of the doped nanowires showed minimal crystal damage. Electrical characterisation of the Ge nanowires was performed to contrast doping activation in thin-body structures with that in bulk substrates. Despite the high As dose incorporation on unpatterned samples, the nanowire analysis determined that the P-based process was the better choice for scaled features.

From Springer description: "We present the design considerations of an autonomous wireless sensor and discuss the fabrication and testing of the various components including the energy harvester, the active sensing devices and the power management and sensor interface circuits. A common materials platform, namely, nanowires, enables us to fabricate state-of-the-art components at reduced volume and show chemical sensing within the available energy budget. We demonstrate a photovoltaic mini-module made of silicon nanowire solar cells, each of 0.5 mm2 area, which delivers a power of 260 μW and an open circuit voltage of 2 V at one sun illumination. Using nanowire platforms two sensing applications are presented. Combining functionalised suspended Si nanowires with a novel microfluidic fluid delivery system, fully integrated microfluidic–sensor devices are examined as sensors for streptavidin and pH, whereas, using a microchip modified with Pd nanowires provides a power efficient and fast early hydrogen gas detection method. Finally, an ultra-low power, efficient solar energy harvesting and sensing microsystem augmented with a 6 mAh rechargeable battery allows for less than 20 μW power consumption and 425 h sensor operation even without energy harvesting."

The junctionless nanowire metal–oxide–semiconductor field-effect transistor (JNT) has recently been proposed as an alternative device for sub-20-nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS-compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an ION/IOFF current ratio of 1.2 × 103 at VD = –1 V and drain-induced-barrier lowering (DIBL) of 87 mV. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A method for cross-sectional doping of individual Si/SiO2 core/shell nanowires (NWs) is presented. P and B atoms are laterally implanted at different depths in the Si core. The healing of the implantation-related damage together with the electrical activation of the dopants takes place via solid phase epitaxy driven by millisecond-range flash lamp annealing. Electrical measurements through a bevel formed along the NW enabled us to demonstrate the concurrent formation of n- and p-type regions in individual Si/SiO2 core/shell NWs. These results might pave the way for ion beam doping of nanostructured semiconductors produced by using either top-down or bottom-up approaches.

Hyperdoping consists of the intentional introduction of deep-level dopants into a semiconductor in excess of equilibrium concentrations. This causes a broadening of dopant energy levels into an intermediate band between the valence and conduction bands.[1,2] Recently, bulk Si hyperdoped with chalcogens or transition metals has been demonstrated to be an appropriate intermediate-band material for Si-based short-wavelength infrared photodetectors.[3-5] Intermediate-band nanowires could potentially be used instead of bulk materials to overcome the Shockley-Queisser limit and to improve efficiency in solar cells,[6-9] but fundamental scientific questions in hyperdoping Si nanowires require experimental verification. The development of a method for obtaining controlled hyperdoping levels at the nanoscale concomitant with the electrical activation of dopants is, therefore, vital to understanding these issues. Here, we show a CMOS-compatible technique based on non-equilibrium processing for the controlled doping of Si at the nanoscale with dopant concentrations several orders of magnitude greater than the equilibrium solid solubility. Through the nanoscale spatially controlled implantation of dopants, and a bottom-up template-assisted solid phase recrystallization of the nanowires with the use of millisecond-flash lamp annealing, we form Se-hyperdoped Si/SiO2 core/shell nanowires that have a room-temperature sub-band gap optoelectronic photoresponse when configured as a photoconductor device.

The integration of high-mobility III–V compound semiconductors emerges as a promising route for Si device technologies to overcome the limits of further down-scaling. In this work, we investigate the possibilities to form InAs nanocrystals in a thin Si layer at laterally defined positions with the help of masked ion beam implantation and flash lamp annealing. In detail, a cladding layer was deposited on a silicon-on-insulator (SOI) wafer and patterned by electron beam lithography in order to serve as an implantation mask. The wafer was subsequently implanted with As and In, followed by flash lamp annealing leading to the formation of InAs nanoparticles in the implanted areas. The structures were investigated by Raman spectroscopy, scanning, and transmission electron microscopy as well as energy-dispersive X-ray spectroscopy. Depending on the size of the implantation window, several, one or no nanoparticle is formed. Finally, the perspectives for using this technique for the local modification of Si nanowires are discussed.

Top-down fabrication of sub-50nm silicon nanowire sensors with various geometries.Excellent performance as backgated junctionless nanowire transistors (JNTs).Very good sensing capabilities.Among the smallest top-down fabricated nanowire sensing devices reported to date. This article reports the fabrication of sub-50nm field effect transistor (FET)-type silicon (Si) nanowire (Si NW) chemical and biological sensing devices with a junctionless architecture, as well as on the initial characterisation of their electrical and sensing performance.The devices were fabricated using a fully complementary metal-oxide-semiconductor (CMOS)-compatible top-down process on silicon-on-insulator (SOI) wafers. The fabrication process was mainly based on high-resolution electron beam lithography (EBL) and reactive ion etching (RIE) but also included photolithography (mix-and-match lithography), thin film deposition by electron beam evaporation, lift-off, thermal annealing and wet etching.The sensing performance of a matrix of nanowire devices, i.e. containing 1, 3 and 20 NWs with lengths of 0.5, 1 and 10µm was examined. Each element of the matrix also contained five devices with different NW widths: 10, 20, 30, and 50nm and 5µm (a Si belt reference device). Electrical characterisation of the devices showed excellent performance as backgated junctionless nanowire transistors (JNTs): high on-currents in the range of 1-10µA and high ratios between the on-state and off-state currents (Ion/Ioff) of 6-7 orders of magnitude. In addition, the results of ionic strength sensing experiments demonstrate the very good sensing capabilities of these devices. To the best of our knowledge, these nanowire sensors are among the smallest top-down fabricated Si NW devices reported to date.

In this chapter, we introduce two specific types of junctionless nanowire transistors (JNTs): (i) silicon-on-insulator (SOI) back-gated JNTs for sensing applications and (ii) germanium-on-insulator (GeOI) top-gated JNTs for digital logic applications. We discuss in detail the suitability of junctionless architecture for these particular applications and present results on device fabrication and characterisation. Back-gated JNTs of 45 different channel geometries (different numbers, lengths, and widths of channel nanowires) have been designed and fabricated with very high precision (down to 10 nm widths of the nanowires) on SOI wafers using a fully CMOS-compatible fabrication process. Electrical characterisation of the fabricated devices has demonstrated their excellent performance as back-gated JNTs. Furthermore, data from pH and streptavidin sensing experiments have proven their good sensing properties. These JNTs are among the smallest top-down fabricated nanowire sensing devices reported to date. Top-gated JNTs with Ge nanowire channels of widths down to 20 nm have been fabricated by a simple CMOS-compatible process on GeOI wafers with a highly p-doped (~1×1019 cm−3) top germanium layer. The fabricated devices have demonstrated decent output and transfer characteristics with relatively high I on /I off current ratios of up to 2.0 × 105 and steep subthreshold slopes of 189 mV/dec. To the best of our knowledge, these are the first reported Ge JNTs.

A 3D, vertically stacked silicon nanowire (SiNW) field effect transistor (FET) featuring a high density array (7×20) of fully depleted channels has been successfully fabricated by a CMOS compatible process on silicon on insulator (SOI) and functionalized for streptavidin detection for the first time. The channels are surrounded by conformal high-κ gate dielectrics (HfO2), and their conductivity can be uniquely tuned by three gates; a backgate (BG) and two symmetrical Pt side gates (SG) through a liquid, offering unique sensitivity tuning with high gate coupling (SS=75 mV/dec, α'=SS60mV/dec/SSmeasured=0.8, with highest sensitivity=93-99%, obtained for I=1 0pA-10nA, in weak inversion) ever published.

A high-gain photodetector based on junctionless MOSEFT has been presented in this work. Tri-gate junctionless nanowire phototransistors were fabricated on (100) silicon-on-insulator wafers with a buried oxide of thickness 145 nm and top silicon layer of thickness 10 nm. The gate stack consisted of a 10 nm SiO2 dielectric and a 50 nm poly-Si gate electrode. The channel length and doping concentration of junctionless n-MOSFETs was 1 μm and 3 × 1019 cm−3, respectively. The dark current of this device measured at room temperature was less than 1 pA. The measured internal gain of the device was about 35 for 860 nm light illumination. The photocurrent was 300 times larger than the dark current for only 30 nW incident power on the nanowire at 300 mV drain bias.

A single step metal assisted etching (MAE) process, utilizing metal ion-containing HF solutions in the absence of an external oxidant, has been developed to generate heterostructured Si nanowires with controllable porous (isotropically etched) and non-porous (anisotropically etched) segments. Detailed characterisation of both the porous and non-porous sections of the Si nanowires was provided by transmission electron microscopy studies, enabling the mechanism of nanowire roughening to be ascertained. The versatility of the MAE method for producing heterostructured Si nanowires with varied and controllable textures is discussed in detail.

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.

An initial top-down process of Germanium nanowires is developed in this work. The Silicon Nitride (Si 3 N 4 ) is used as a hard mask to obtain a stable surface for lithography and a resistive mask for etch. The electron-beam lithography (EBL) is utilized for patterning the nanowires with Hydrogen Silsesquixane (HSQ) as a negative photoresist. Several different etch conditions are examined to transfer the patterns into the substrate.

Silicon nanowire (SiNW) field effect transistors (FETs) have been widely investigated as biological sensors for their remarkable sensitivity due to their large surface to volume ratio (S/V) and high selectivity towards a myriad of analytes through functionalization. In this work, we propose a long channel (L > 500 nm) junctionless nanowire transistor (JNT) SiNW sensor based on a highly doped, ultrathin body field-effect transistor with an organic gate dielectric epsilon(r) = 1.7. The operation regime (threshold voltage V-th) and electrical characteristics of JNTs can be directly tuned by the careful design of the NW/Fin FET. JNTs are investigated through 3D Technology Computer Aided Design (TCAD) simulations performed as a function of geometrical dimensions and channel doping concentration N-d for a p-type tri-gated structure. Two different materials, namely, an oxide and an organic monolayer, with varying dielectric constants er provide surface passivation. Mildly doped N-d = 1 x 10(19) cm(-3), thin bodied structures (fin width F-w < 20 nm) with an organic dielectric (epsilon(r) = 1.7) were found to have promising electrical characteristics for FET sensor structures such as V-th similar to 0 V, high relative sensitivities in the subthreshold regime S > 95%, high transconductance values at threshold g(m),(Vfg=0V) > 10 nS, low subthreshold slopes SS similar to 60 mV/dec, high saturation currents I-d,I-max similar to 1-10 mu A and high I-on/I-off > 10(4)-10(10) ratios. Our results provide useful guidelines for the design of junctionless FET nanowire sensors that can be integrated into miniaturized, low power biosensing systems. (c) 2013 Elsevier B.V. All rights reserved.

Silicon nanowire (Si NW) sensors have attracted great attention due to their ability to provide fast, low-cost, label-free, real-time detection of chemical and biological species. Usually configured as field effect transistors (FETs), they have already demonstrated remarkable sensitivity with high selectivity (through appropriate functionalisation) towards a large number of analytes in both liquid and gas phases. Despite these excellent results, Si NW FET sensors have not yet been successfully employed to detect single molecules of either a chemical or biological target species. Here we show that sensors based on silicon junctionless nanowire transistors (JNTs), the simplest possible transistors, are capable of detecting the protein streptavidin at a concentration as low as 580 zM closely approaching the single molecule level. This ultrahigh detection sensitivity is due to the intrinsic advantages of junctionless devices over conventional FETs. Apart from their superior functionality, JNTs are much easier to fabricate by standard microelectronic processes than transistors containing p–n junctions. The ability of JNT sensors to detect ultra-low concentrations (in the zeptomolar range) of target species, and their potential for low-cost mass production, will permit their deployment in numerous environments, including life sciences, biotechnology, medicine, pharmacology, product safety, environmental monitoring and security.