Search

The design of a high-performance Dielectrically Modulated Field Effect Transistor (DMFET) with smaller device dimension (channel length ≤ 100nm) has recently drawn significant research attention for point-of-care (POC) diagenesis applications. Driven by this paradigm, a Hetero-Gate Metal Dielectrically Modulated Junction-Less Nanotube Field Effect Transistor (DM-JLNFET) architecture is introduced and systematically investigated for label-free electrochemical biosensing application with the help of extensive numerical device simulations. The DM-JLNFET is carefully designed to exploit the advantages of superior gate control over channel electrostatics and electron injection component as well as strong immunity towards the short channel effects that lead to a notably high sensing performance compared to its conventional counterparts. In this context, the underlying physics of the transduction mechanism is analyzed in detail based on the device electrostatics and the carrier transport mechanism. The sensing performance of the proposed biosensor is quantified in terms of the drain current and threshold voltage sensitivities, which represents the relative modulations in these parameters with biomolecule conjugation. Typically, the DM-JLNFET exhibits a drain current and threshold voltage sensitivities as high as 1×10 12 and 0.70, respectively, for biomolecule dielectric constant above 2. Furthermore, the sensing performance demonstrates strong immunities towards non-uniform cavity occupancy. Finally, extensive comparative performance analysis with Dielectrically Modulated Nanowire Field Effect Transistor (DM-NWFET) is performed. The results exhibit that the proposed DM-JLNFET can offer more than 100% and eight orders of magnitude improvements in the threshold voltage and drain current sensitivities, respectively, for a range of small biomolecule dielectric constants.

This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved Ion/Cgg. The improvement in read (write) access time is ~22% (17%) and ~9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (Ion/Ioff) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (~0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell. [ABSTRACT FROM AUTHOR]

This paper investigates the performance of 6 T SRAM cell using high- K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high- K gate dielectric enhances the delay performance of the JLSiNTFET based 6 T SRAM cell. Read access time (RAT) and write access time (WAT) improves by ∼18% and ∼20% when TiO 2 is used as gate dielectric instead of SiO 2 . The hold, read, and write SNMs (static noise margin) of the 6 T SRAM cell also improves marginally by the use of high- K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM (RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (T I ). However, the improvement in read access times (RAT) & write access time (WAT) degrades at higher T I . Thus, high- K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT-FET based 6 T SRAM cell. [ABSTRACT FROM AUTHOR]

This paper investigates the analog/RF performance of inner gate engineered junctionless silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric drain/source DS-JLSiNT-FETs (inner gate extended from one end of nanotube to other end covering both drain and source region) gets improved when the inner gate of nanotube (NT) covers only either drain and channel regions (D-JLSiNT-FETs) or source and channel regions (S-JLSiNT-FETs) because of reduced total gate capacitance. The improvement in cut-off frequency (f T ) in D-JLSiNT-FETs is ∼45% whereas in S-JLSiNT-FETs is ∼23% as compare to DS-JLSiNT-FETs. However, the percentage improvement in maximum oscillation frequency (f MAX ) is more in S-JLSiNT-FETs. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity ( EI ) is reduced resulting in degraded intrinsic gain (A V ). However, the deterioration in A V is almost minimal (∼0.4 dB) for D-JLSiNT-FETs as compared to DS-JLSiNT-FETs but the deterioration in A V is aggravated to ∼22 dB for S-JLSiNT-FETs. The up scaling of Source/Drain extension length improves the performance of D-JLSiNT-FETs but degrade the performance of S-JLSiNT-FETs when compared to DS-JLSiNT-FETs. The improvement in f T and f MAX in D-JLSiNT-FETs as well as in S-JLSiNT-FETs are pronounced with outer gate length scaling when compared to DS-JLSiNT-FETs. [ABSTRACT FROM AUTHOR]

• The temperature sensitivity on analog/RF FOMs of JL-SiNT-FET has been checked. • The temperature drop improves the analog/RF FOMs of all the configurations of JL-SiNT-FET by substantial amount. • ΔF = F T=100 - F T=400 , where F is the analog/RF FOMs is almost same in all the configurations. • The D-JL-SiNT-FET configuration is best among all three configurations at all temperatures. This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (A V) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (f T), maximum oscillation frequency (f MAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = F T=100 - F T=400 , where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations. [ABSTRACT FROM AUTHOR]