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SUMMARY Translation Lookaside Buffers (TLBs) can play a critical role in improving the performance of emerging parallel workloads. Most current chip multiprocessor systems include multilevel TLBs and provide support for superpages both at the hardware and software level. Judicious use of superpages can significantly cut down the number of TLB misses and improve overall system performance. However, indiscriminate superpage allocation results in page fragmentation and increased application footprint, which often outweigh the benefits of reduced TLB misses. Previous research has explored policies for smart allocation of superpages from an operating system perspective. This paper presents a compiler-based strategy for automatic and profitable memory allocation via superpages. A significant advantage of a compiler-based approach is the availability of data-reuse information within an application. Our strategy employs data-locality analysis to estimate the TLB demands for both single-threaded and multi-threaded programs and uses this metric to apply selective superpage allocation. Apart from its obvious utility in improving TLB performance, this strategy can be used to improve the effectiveness of certain data-layout transformations and can be a useful tool in benchmarking and automatic performance tuning. We demonstrate the effectiveness of this strategy with experiments on three multicore platforms on a workload that contains both sequential and parallel applications. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The emergence of chip-multiprocessor systems has dramatically increased the performance potential of computer systems. However, harnessing the full potential of these systems depends largely on the effectiveness of system software, such as compilers, in exploiting the on-chip parallelism. Additionally, since the amount of parallelism extracted by a compiler is directly influenced by the selection of the algorithm, algorithmic choice also plays a critical role in achieving a high fraction of peak performance. Hence, in the era of multicore computing, it is imperative that we re-evaluate and rethink algorithms for key problem domains. This paper investigates the impact of algorithmic choice on the performance of parallel implementations of the integral knapsack problem on multicore architectures. The study considers two classes of algorithms and several algorithmic variants and evaluates each implementation based on a variety of performance metrics including data locality and sharing, granularity of parallelism and scalability. The paper presents experimental results that show how each performance factor is affected by the selection of algorithm, changes in the input data-set and variations in architectural characteristics such as cache capacity and degree of cache sharing. [ABSTRACT FROM PUBLISHER]