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In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be implemented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and provides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, showing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/oC from -40 to +85oC, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V.

This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from −40 to 125 °C, a power supply rejection ratio (PSRR) of −54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm2.

In this paper, we propose an ultra-low power compact 3-transistor voltage reference capable of operating at ultra-low supply voltages. The proposed circuit is based on the self-cascode MOSFET (SCM), which provides a reference voltage proportional to the threshold voltage ( $V_{T}$ ) difference of the two NMOS transistors that compose it. Reverse short-channel and narrow-width effects are explored to obtain such $V_{T}$ difference while using the same type of transistor. Ultra-low power operation and low line sensitivity is achieved by biasing the SCM with a zero- $V_{T}$ (native) transistor, also leading to an area efficient design. To show its versatility, three versions of the proposed circuit were fabricated in a standard 0.13- $\mu \text{m}$ CMOS process. Measurement performed over five samples showed an average temperature coefficient of 150–1500 ppm/°C. Minimum supply voltages of 0.12–0.4 V was observed while providing reference voltages around tens of mV. The proposed circuits consume 0.33–50 pW at room temperature and minimum supply voltage. The occupied area for any version is less than 0.0012 mm2.

In this paper, a self-biased temperature-compensated CMOS voltage reference operating at picowatt-level power consumption is presented. The core of the proposed circuit is the self-cascode MOSFET (SCM) and two variants are explored: a self-biased SCM (SBSCM) and a self-biased NMOS (SBNMOS) voltage reference. Power consumption and silicon area are remarkably reduced by combining subthreshold operation with a self-biased scheme. Trimming techniques for both circuits are discussed aiming at the reduction of the process variations impact. The proposed circuits were fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. Measurement results from 24 samples of the same batch show that both circuits herein proposed can operate at 0.45/0.6 V minimum supply voltage, consuming merely 55/184 pW at room temperature. Temperature coefficient (TC) around 104/495 ppm/°C across a temperature range from 0 to 120 °C was measured. Employment of a trimming scheme allows a reduction of the average TC to 72.4/11.6 ppm/°C for the same temperature range. Both variants of the proposed circuit achieve a line sensitivity of 0.15/0.11 %/V and a power supply rejection better than −44/−45 dB from 10 to 10 kHz. In addition, SBSCM and SBNMOS prototypes occupy a silicon area of 0.002 and 0.0017 mm2, respectively.

Electromagnetic interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite power supply rejection (PSR). The design of a 90-dB PSR 4-dBm EMI-resistant NMOS-only voltage reference is herein presented. The voltage reference is designed based on the zero-temperature-coefficient transistor operating point. The high PSR is obtained using zero- $V_{T}$ transistors as active loads in the open and feedback loop of the circuit. Two versions, using standard $V_{T}$ and low-power $V_{T}$ transistors, were designed in a 130-nm CMOS process. Both are designed using the same thermal compensation principle. The circuits occupy 0.014 and 0.006 mm $^{2}$ of silicon area while consuming around 1.15 and 0.156 $\mu$ W at 27 $^\circ$ C, respectively. Postlayout simulations present a reference voltage of 206 and 450 mV with an average temperature coefficient of 321 and 86 ppm/ $^\circ$ C (1000 samples), under a temperature range from $-$ 55 to 125 $^\circ$ C. An EMI source of 4 dBm (1 $\text{V}_{\text{pp}}$ ) injected in the power supply, according to the direct power injection standard, yields $-$ 0.17% and $-$ 0.1 ${\%}$ of the maximum dc shift and 822 and 950 $\mu \text{V}_{\text{pp}}$ of the maximum peak-to-peak ripple for the standard $V_{T}$ and low-power $V_{T}$ implementations, respectively.

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3 V up to 1.2 V and outputs three different reference voltages using Standard- $V_{T}$ (SVT), Low- $V_{T}$ (LVT), and Zero- $V_{T}$ (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13- $\mu \text{m}$ CMOS process show a worst-case normalized standard deviation $(\sigma /\mu)$ of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/°C over the full commercial temperature range. At room temperature (25 °C), line sensitivity in the ZVT VR is just 1.3%/100 mV, over the whole supply range. The proposed reference draws around 5 $\mu \text{W}$ and occupies 0.014 mm2 of silicon area.

This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate with supply voltages as low as 0.45 V while consuming tens of pW. The voltage reference is generated through the self-cascode MOSFET (SCM) using transistors with different threshold voltages and is implemented in a way that the SCM itself composes the bias circuitry. The proposed topology was implemented in a standard 0.18 μm CMOS process and post-layout simulation results in a reference voltage of 248 mV with temperature coefficient around 7 ppm/oC for the 0 oC to 125 oC range, while consuming 93 pW at room temperature with 0.45 V of supply voltage. The occupied silicon area is 0.002 mm2.

This paper presents a MOS-only high power supply rejection (PSRR) voltage reference with a very low temperature coefficient (TC) that consumes only tens of nano-Watt. It is composed by a threshold voltage monitor circuit with no resistors, cascaded with a thermal voltage generator, adequate for fabrication in standard processes. Since the MOS transistors operate in subthreshold and near-threshold regimes the current consumption is very low. The operation of the circuit is analytically described and a design methodology is proposed. Post-layout simulations for a design in a 130 nm CMOS process are presented, resulting a reference voltage around 670 mV with a best case TC of 1.5 ppm/°C for the −40 to +125 °C range and an average TC of 20 ppm/°C over process variations, untrimmed. A very low sensitivity to VDD is achieved, resulting a PSRR lower than −71 dB at 100 Hz and a line sensitivity (LS) lower than 576 ppm/V for a supply range from 1 to 3 V. The area is very small, 0.0084 mm2 including the start-up stage.

In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ< 3.3% and that 90% of the samples present TC

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

Electromagnetic Interference (EMI) disturbances coupled in the power supply of voltage and current references can severely degrade their performance, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant NMOS-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Post-layout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/°C, for the temperature range from −55 to 125 °C. An EMI source of 4 dBm (1 V pp ) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum dc shift and Peak-to-peak ripple of −0.17 % and 822 μV pp , respectively.

Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from −55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of −0.17 % and 822 μVpp, respectively.

This work presents a high PSRR nano-watt resistorless thresh old voltage (VTo) monitor circuit that can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications such as fabrication process monitoring and verification. In this circuit design the MOS transistors operate in subthreshold and near-threshold regimes, the circuit analysis is based on a current-voltage relationship derived from a continuous physical MOSFET model, valid from weak to strong inversion. The bias condition is established from the equilibrium between two self-cascode cells operating at different inversion levels, and the high PSRR results from a high gain feedback path. The circuit is MOSFET-only, and can be implemented in any standard digital CMOS process. Post-layout simulations show that it operates with less than 1 V of power supply, consuming only tens of nW, and resulting in a VT0 error lower than 1%, when compared to its modeling value, for a −40 to +125°C temperature range. A very high rejection to VDD variation is achieved in this design, with PSRR lower than −63.9 dB at 100 Hz, and a line sensitivity lower than 252 ppm/V was found for a supply range from 1 V to 3 V. Monte-Carlo simulations are presented to evaluate the fabrication variability sensitivity, presenting a maximum error of 4% for a 3a spread range. The circuit area is very small, around 0.0047 mm2 including the start-up stage.

This work presents a self-biased MOSFET threshold voltage V T0 monitor. The threshold condition is defined based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit consists in balancing two self-cascode cells operating at different inversion levels, where one of the transistors that compose these cells is biased at the threshold condition. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. We propose a process independent design methodology, evaluating different trade-offs of accuracy, area and power consumption. Schematic simulation results, including Monte Carlo variability analysis, support the V T0 monitoring behavior of the circuit with good accuracy on a 180 nm process.

Digital and analog ICs generally rely on the concept of matched behavior between identically designed devices. Time-independent variations between identically designed transistors, called mismatch, affect the performance of most analog and even digital MOS circuits. This article focuses on the analysis of mismatch in MOS transistors resulting from random fluctuations of the dopant concentration, first studied by Keyes. Today, we recognize these fluctuations as the main cause of mismatch in bulk CMOS transistors.

The MOSFET Zero Temperature Coefficient (ZTC) condition is a strategy that can be used to implement low temperature sensitivity circuits, such as current and voltage references. This condition is usually analyzed using the strong inversion quadratic MOSFET model. In this work we use a different approach, based on a continuous MOSFET model that can predict its behavior from weak to strong inversion. Based on this analysis, we verify that the ZTC point occurs from moderate to strong inversion for any CMOS process, since this point must occur for gate-source voltages larger than one threshold voltage. Also, a resistorless switched capacitor current reference based on the ZTC condition (ZSCCR), presenting low temperature coefficient (TC), is presented. The ZSCCR is designed in a 180 nm process, resulting a reference current of 5.88 µA under a supply voltage of 1.8 V, and occuping a silicon area around 0.010mm2. Results from circuit simulation show an effective temperature coefficient (TC eff ) of 60 ppm/°C from −45 to +85 °C and a power consumption of 63 µW.

The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and RF circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed by a diode-connected MOS transistor operating near the ZTC condition that is biased by a proportional-to-absolute-temperature (PTAT) current reference implemented with Schottky-diodes. The ZTC condition is analysed using a continuous MOSFET model that is valid from weak to strong inversion and the circuit behaviour is described by theoretical expressions. Our reference circuit is designed for 3 versions: each with MOSFETs of different threshold voltage (standard-VT, low-VT, and zero-VT), all available in the 130 nm CMOS process used. These designs result in three different and very low reference voltages: 312, 237, and 51 mV. All 3 designed reference operate in the range of 0.45 to 1.2 V of supply voltages, consuming 1 uA of typical supply current. Post-layout simulations present a Temperature Coefficients (TCs) of 214, 372, and 953 ppm/°C in a temperature range from -55 to 125°C, respectively. Monte-Carlo simulations show the fabrication variability impact on the circuit performance. The voltage reference was designed in a 130 nm process and it uses 0.014 mm2 of silicon area.

The necessary conditions to design MOSFET transconductors with low temperature dependence are analysed and defined in this paper. Transconductors, or Gm circuits, are fundamental blocks used to implement adjustable filters, multipliers, controlled oscillators, amplifiers and a large variety of analog circuits. Temperature stability is a must in such applications, and herein we show a strategy that can be used to improve the temperature stability of these transconductors by biasing MOSFETs at transconductance zero-temperature condition (GZTC). This special bias condition is analysed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are proposed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits were simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

This work presents a self-biased MOSFET threshold voltage V T0 extractor circuit. Its working principle is based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nW. Post-layout simulation results show that the extracted V T0 has an error inferior to 1.3%, when compared to the theoretical value, for a −40 to 125°C temperature range. We present variability results from Monte Carlo simulations that support the extracting behavior of the circuit with good accuracy. The occupied silicon area is 0.0076 mm2 in a 0.13µm CMOS process.

In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/oC for the 0 to 125 °C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2.

A self-biased current reference based on the MOSFET Zero Temperature Coefficient (ZTC) condition is presented. It can be implemented in any CMOS process and it provides a simple alternative to design a reference current suitable for low TC biasing. This topology was designed in a 0.18 μm process to generate 5 μA under a supply voltage from 1.4V to 1.8 V, spending a silicon area around 0.010mm2. From circuit simulations, the current reference is estimated to have a temperature coefficient (TCeff) of 15 ppm/°C from -40 to +85 °C and a fabrication sensitivity of σ/μ = 4.5%, including average process and local mismatch variability. The power supply sensitivity resulted around 1%V for this new reference.

This paper presents a new approach for accurate M-2M MOSFET digital-to-analog converter (DAC) design. It describes a complete design methodology, where DAC inaccuracy is related to transistor geometry and bias through a powerful physics-based MOSFET mismatch model, very useful for hand design. Short-channel effects are also taken into account. Two versions of the converter were implemented in a 0.35 mum 3.3 V CMOS technology, and corroborate the theoretical development with statistical experimental results.

Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significantly impact manufacture costs by decreasing yield and so by including extra-circuits for adjustment. In this paper we propose a design methodology based on the Pelgrom's MOS transistor-mismatching model devices. Our main objective is to calculate the size of each component considering their relation between area and mismatching. Therefore, in order to validate our proposal methodology, we used as a design target a bandgap reference circuit fabricated in 0.35 mum CMOS technology. Its temperature coefficient attains an average value of 40ppm/degC and an average output voltage of 1,20714V. It also includes a straightforward 4-bits trim circuit to achieve more process independence variation. As a result of our methodology, the considerable area of 400 times 350 mum2 was occupied due to our matching design requirements

Most of the new generation compact models for the MOSFET have many commonalities since they are based on the same main approximations: gradual channel, charge-sheet, and depletion charge linearization. In this study we show that if we include some additional physics-consistent conditions for the MOSFET equations we obtain a very compact model that we call the advanced compact MOSFET (ACM) model. The core ACM model, design-oriented equations, parameter extraction, and a design example are presented.

This paper describes a test circuit for intensive characterization of MOS transistors mismatch. It aggregates analog switches, a shift register and a reference circuit, as well as the matrix of 1296 transistors to be tested. This circuit was integrated in a 0.35 mm bulk technology, and was designed to give experimental support for our MOSFET mismatch model. The test chip was characterized over a wide range of operation conditions, from weak to strong inversion, from linear to saturation region, allowing the analysis of MOSFET mismatch from bias, process and geometric parameters.

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters.

Postprint This work presents an approach for accurate MOS transistor matching calculation. Our model, which is based on an accurate physics-based MOSFET model, allows the assessment of mismatch from process parameters and valid for any operating region. Experimental results taken on a test set of transistors implemented in a 1.2 /spl mu/m CMOS technology corroborate the theoretical development of this work.