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A thermally stable single-transistor neuron (1T-neuron) that uses a vertical nanowire Si MOSFET is demonstrated. The concept of a single-transistor latch (STL) in a MOSFET, which is used to mimic neural firing in a biological neuron, is sensitive to the temperature (${T}$) because it generally occurs due to impact ionization (I.I.). As an alternative to the thermally sensitive I.I., thermally insensitive band-to-band tunneling (BTBT) is used to enable the STL to function. Neuronal operation with thermal stability is thereby achieved. It is verified in spiking neural network (SNN) simulations that the recognition ability of handwritten digits in the MNIST dataset was not sensitive to ${T}$. [ABSTRACT FROM AUTHOR]

A CMOS ternary logic is demonstrated using a biristor threshold switch (BTS). A biristor, which can operate as a threshold switch, encloses a two-terminal n-p-n structure with a floating p-base region akin to a base-open BJT. The switching mechanism is a single-transistor latch (STL). When a BTS and a MOSFET are serially connected, three stable states are sustained for a ternary logic system. Compared to other ternary devices, static power can be greatly reduced due to low leakage current of the BTS. In addition, the BTS and the MOSFET were co-integrated due to their homeomorphy for fabrication simplicity, i.e., because the BTS has a structure identical to that of a MOSFET, unlike other threshold switches. [ABSTRACT FROM AUTHOR]

A junctionless single-transistor neuron (JT-neuron) composed of vertically stacked multiple nanowires (NWs) with a gate-all-around structure (GAA) is demonstrated to drive more synapses compared with a single NW junctionless GAA MOSFET for neuromorphic hardware. A homogeneously doped junctionless structure is advantageous for fabrication simplicity compared with a heterogeneously doped junction structure, which has been widely used as an inversion mode transistor. The nature of the junctionless MOSFET is robust to punchthrough or drain-induced barrier lowering (DIBL) in a scaled transistor. Furthermore, vertically stacked multiple NWs are favorable for improving the ON-state current to be able to derive more synapses and higher packing density without sacrifice of the footprint area compared with a laterally deployed NW structure. To evaluate the feasibility of applying the JT-neuron to a spiking neural network (SNN), experimental-based simulations are performed. A recognition accuracy of 91.7% is achieved for Modified National Institute of Standards and Technology (MNIST) handwritten digits. [ABSTRACT FROM AUTHOR]

Stress-induced damage in a MOSFET can be cured by Joule heating, which can be produced by an intentional forward junction current (${I}_{\textbf {FWD}}$). This curing effect can be further enhanced by the simultaneous application of gate biasing, which does not influence the ${I}_{\textbf {FWD}}$. A MOSFET was intentionally degraded by harsh hot-carrier injection (HCI) then the damage was cured and nearly returned to its pristine state. The improved self-curing effect was quantitatively verified using low-frequency noise (LFN) analyses. Self-curing by internal heat from the ${I}_{\textbf {FWD}}$ more effectively cured the HCI damage than a nonself-curing using external heat from a hot chuck. [ABSTRACT FROM AUTHOR]

The number of interface traps (${N}_{\textit {it}}$) in a gate-all-around (GAA) MOSFET that harnesses an inherent floating body, was analyzed by using the synchronized optical charge pumping (SOCP) technique. By synchronizing control timing between the MOSFET operation and optical stimulation by light, holes generated by light illumination dominantly vanished, due to surface recombination with interface traps, rather than bulk recombination in a silicon nanowire and source/drain back-diffusion. This SOCP characterized the ${N}_{\textit {it}}$ without the aid of any additional specified test structure. To demonstrate an application, the amount of interface traps originating from off-state stress was quantitatively extracted by the SOCP. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) characteristics under OFF-state stress (OSS), which degrade device performance, were investigated in n-channel MOSFETs. The power spectral density (PSD) was analyzed by investigating the LFN and the border traps located in the gate oxide were extracted along a depth direction perpendicular to the silicon (Si) channel surface. The holes generated by band-to-band tunneling (BTBT) in the overlap region between a drain and a gate were found to be more detrimental to device performance than channel hot-carriers created by impact ionization. [ABSTRACT FROM AUTHOR]

High-pressure (HP) deuterium (D2) annealing was applied to a gate-all-around (GAA) MOSFET to improve device reliability and memory performance. The structure had gate dielectrics of oxide–nitride–oxide (ONO), which completely straddled vertically stacked multiple silicon nanowires (Si-NWs) with n+ poly-Si gates. The HP D2 annealing was effective for the vertically stacked GAA MOSFET as it was for a conventional planar MOSFET. In addition, the resistance of the n+ poly-Si gate was also reduced after the HP D2 annealing. This is attributed to the passivation of defects among adjacent poly-Si grains by the HP D2. The reduced gate resistance (RG) is advantageous for decreasing RC delay. Direct characterizations of dc I – V and analyses of ac low-frequency noise (LFN) supported the abovementioned behaviors. [ABSTRACT FROM AUTHOR]

For the first time, a single transistor neuron (1T-neuron) with an independently accessed double-gate structure is demonstrated for excitatory-inhibitory function, and control of the firing threshold voltage (${V}_{{\text {T,firing}}}$). The double-gate is composed of a primary gate and a secondary gate. The former is to determine an excitatory and inhibitory state as a toggle switch and the latter is to dynamically adjust ${V}_{\text {T,firing}}$ for homeostasis to sustain reliable neuromorphic operation. In addition to its conventional excitation function, the newly implemented inhibition function improves the energy efficiency of the neuromorphic network. The tunable threshold voltage for firing maintains homeostasis, even for high or low transmitted signals that are out of a desired spiking frequency range. [ABSTRACT FROM AUTHOR]

The gate-induced drain leakage (GIDL) current is one of the major leakage sources in a dynamic random-access memory (DRAM) cell transistor. In addition to band-to-band tunneling (BTBT), which causes GIDL in the gate-to-drain overlap region, the generation of interface traps in the gate dielectric increases the GIDL current by trap-assisted two-step tunneling (TATT). In this article, the influence of OFF-state stress on the generation of the interface traps, which deteriorates GIDL, was quantitatively analyzed with charge pumping (CP) characterization method in buried-channel array transistors (BCATs) for DRAM cells. The applied stress increased the GIDL current while simultaneously degrading device performance including such as transconductance (gm) and ON-state current (ION), due to the generation of the interface traps. By using the CP characterization, the interface traps were spatially profiled along the gate-to-drain overlap region in the junction. Trap distribution inside the energy bandgap was also characterized. [ABSTRACT FROM AUTHOR]

Gate oxide aging in a gate-all-around (GAA) FET fabricated on a bulk substrate was successfully cured by gate-induced drain leakage (GIDL) current. High level of GIDL current flows during the off-state cures the gate oxide aging by hot-carrier injection (HCI). The recovery behaviors were analyzed by tracing changes in the device parameters. Especially, it was found that the curing was not associated with the electric field or created holes under the bias conditions for GIDL, but was associated with the elevated temperature. The GIDL recovery requires neither extra apparatus for Joule heating nor circuit modification. This work can be useful for various FETs which have high off-state current. [ABSTRACT FROM AUTHOR]

Device degradation caused by gate oxide damage in a FinFET on silicon-on-insulator is recovered using punchthrough current via a silicon fin. As the high level of drain current flows under a punchthrough mode, localized Joule heat driven by drain current, enough to anneal the gate oxide, is induced in the channel. This selectively cured localized damage in the FinFET. The dependence of recovery on the gate length, substrate material underneath the channel, and the proper range of annealing voltage are investigated. [ABSTRACT FROM PUBLISHER]

The hot-carrier degradation of the junctionless mode (JM) and the inversion mode (IM) of five-story vertically integrated gate-all-around (GAA) MOSFETs is investigated for the first time. It is found that the degradation of drain current induced by the hot-carrier injection (HCI) in the JM-FET is less than that in the IM-FET for the same dimensions and bias conditions, because of the bulk conduction mechanism of the JM-FET, which is in contrast to surface conduction of the IM-FET. The results are obtained using electrical measurements and numerical simulations. The analysis of how HCI affects the lifetime reliability of vertically integrated GAA MOSFETs is of great importance for ultimate scaling of the silicon transistor. [ABSTRACT FROM PUBLISHER]

Aluminum oxynitride (AlON) is investigated as a germanium oxide (GeO) desorption barrier layer for Ge MOSFETs. Interface and border traps in the AlON/GeO2/Ge gate-stack are discussed in detail and compared with those in the Al2O3/GeO2/Ge gate-stack via MOS and MOSFET structures. Although the interface traps remain the same for AlON and Al2O3 in the gate stacks, the AlON gate-stack exhibits a reduced border trap, which results in improved reliability over the Al2O3 gate-stack. This is supported by both the charge-trapping and low-frequency noise analyses. [ABSTRACT FROM PUBLISHER]

A technique for achieving tunable threshold voltage ( \textV\mathrm{ TH}) is investigated in a gate-all-around device, which is a representative floating body structure. For this concept, the in-plane gate is designed to be both a driving gate and a control gate. The control gate governs the potential distribution along the gate electrode, which acts as a built-in voltage divider in the MOSFET. During the \textV\mathrm{ TH} tuning by the control gate, there is no electrical performance degradation, and modulation of \textV\mathrm{ TH} follows a nearly perfect linear tendency. The results are verified by the electrical measurements of the fabricated device and a multi-physics simulator. [ABSTRACT FROM AUTHOR]

A shift in threshold voltage caused by total ionizing dose (TID) is problematic in the MOSFET, especially in aerospace applications. Unlike traditional methods to minimize damage from TID, in this letter, a novel electro-thermal annealing method to cure the TID-induced damage is demonstrated for the first time. In this concept, the conventional hardening or shielding techniques are not used. In a gate-all-around MOSFET structure, dual gate electrodes were employed as an embedded nanowire heater to generate localized Joule heat, which can anneal insulating layers, including gate oxide and spacer. With the Joule heat, trapped positive charges produced by the TID were neutralized within 200 ms. A damaged device with a radiation-induced threshold voltage shift was repaired to the level of a fresh pristine device. [ABSTRACT FROM PUBLISHER]

Thermal engineering assisted by electrical annealing was applied to enhance the device performance of a gate-all-around (GAA) silicon nanowire (Si-NW) transistor. The ON-state current is increased by four times. Joule heating was produced in a Si-NW by electrical biasing. The heating was concentrated on both edges of the gate, which served as a heat sink, effectively lowering the parasitic external resistance of the GAA Si-NW transistor. The electrical biasing gives rise to a thermal annealing effect on a selected device and to all devices connected by a common biasing electrode. The evidence reported in our previous work regarding current-induced oxidation by Joule heating in a Si-NW was also observed in the measured transfer characteristics of the GAA Si-NW transistor in this paper. [ABSTRACT FROM PUBLISHER]

Device degradation induced by hot-carrier injection was repaired by electrical annealing using Joule heat through a built-in heater in a gate. The concentrated high temperature anneals the gate oxide locally and the degraded device parameters are recovered or further enhanced within a short time of 1 ms. Selecting a proper range of repair voltage is very important to maximize the annealing effects and minimize the extra damages caused by excessive high temperature. The repairing voltage is related to the resistance of the poly-Si gate according to the device scaling. [ABSTRACT FROM PUBLISHER]

A general potential model is proposed for all types of double-gate junctionless FETs (DGJL-FETs), i.e., the symmetric versus asymmetric DG structures and the tied versus untied DG structures. The potential model is obtained with a simple form through a 2-D Poisson’s equation based on the assumption that the vertical channel potential is approximated to a cubic function of the position in order to consider all types of DGJL-FETs. An analytical threshold voltage ( VT) equation via the potential model is derived with the gate voltage when the sum of the depletion widths from the front-gate and the back-gate equals the body thickness. The analytic solution of VT shows good agreement with the simulation results down to a channel length <20 nm. The variability of VT is analyzed for various device parameters. The back-gate effect of the untied DG structure is also investigated. [ABSTRACT FROM AUTHOR]

The influence of the total ionizing dose (TID) on sub-100 nm gate-all-around (GAA) MOSFETs is investigated through experiments and numerical simulations. Particularly, the TID effect is explored for various gate lengths and radiation doses. The radiation-induced charges and traps under the gate spacer result in changes of the device characteristics and is a dominant factor to cause the device degradation. This phenomenon is experimentally examined by the junction modification of GAA MOSFETs and supported by three-dimensional numerical simulations. [ABSTRACT FROM AUTHOR]

An analytical threshold voltage model for a junctionless double-gate MOSFET with localized charges is developed. The model is derived based on 2-D Poisson's equation with parabolic potential approximation. The proposed model is verified by device simulation results. Threshold voltage dependencies on various device parameters are also analyzed. The proposed model can be used to estimate the threshold voltage degradation as caused by hot carrier effects and to provide a guideline for the optimization of junctionless transistors. [ABSTRACT FROM AUTHOR]

A metal-oxide-semiconductor field-effect transistor (MOSFET), which is an elementary unit of microelectronics, was repaired by self-powered electro-thermal annealing with the aid of a wind-driven triboelectric nanogenerator (TENG). It was thermally cured by Joule heat that originated electrically from the MOSFET itself. The configuration of the self-curable system is composed of a MOSFET with an embedded built-in Joule heater and a wind-driven TENG. This self-curable feature is attractive for the construction of remote wireless sensor networks, is capable of sustainable operation for long-term use, has high immunity against external environmental stress as well as internal operation stress, and can reduce labor during the periodic replacement of power sources. • Self-powered electro-thermal annealing was performed to cure the damaged electronic devices. • Electrical output of triboelectric nanogenerator was firstly used as Joule heat generation. • The electronic device was successfully cured by the SP-ETA from plural damage factors: γ-ray and hot carrier injection. • The Self-powered electro-thermal annealing was also verified at charge-trap based flash memory devices. [ABSTRACT FROM AUTHOR]

Gate dielectric degradation caused by off-state stress (OSS) and positive-bias temperature instability (PBTI) was analyzed in terms of charge trapping inside the gate dielectric and at the interface. Under the same degree of stress voltage, the OSS damage caused more degradation of threshold voltage (V T) than the PBTI damage. When the two stresses were alternately applied to an n-channel MOSFET, they effectively produced a leftward shift in the V T. This was because a greater negative V T shift was produced by the OSS and a less positive V T shift was produced by the PBTI. By analyzing the characteristics of the gate induced drain leakage (GIDL), it was determined that charge trapping inside the gate dielectric was more localized on the drain side than on the source side after OSS, but was distributed at a relatively similar level along the channel length direction after PBTI. To analyze the interface traps caused by OSS and PBTI, charge pumping (CP) measurements were conducted to map their lateral distribution along the channel direction. The PBTI-induced interface traps were found to be symmetrically distributed on the source side and drain side, while the OSS-induced interface traps were more concentrated toward the drain side. [ABSTRACT FROM AUTHOR]