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A single-event burnout (SEB) reliability and hardening method for 1.7-kV 4H-SiC power VDMOSFET under high liner energy transfer (LET) value range is proposed and researched by the 2-D numerical simulation. Compared with the conventional VDMOSFET with N-type multi-buffer layers, the hardened VDMOSFET not only ensures that the forward conduction capability does not deteriorate, but also reduces the peak electric field under breakdown voltage from 3.62 MV/cm to 2.98 MV/cm. The advantage of the hardened structure is providing a hole leakage path and increasing the contact area between the source metal and the N+ source, eliminating the effect of electron-hole pairs generated by heavy ion strike on the device, thus improving the SEB performance significantly. In addition, this fabricating technology is compatible with the current technological processes. This hardened structure provides a great potential in aerospace application. [ABSTRACT FROM AUTHOR]

This article presents the 2-D numerical simulation results of the heavy-ion-induced leakage current degradation and single-event burnout (SEB) in the rated 1.2-kV silicon-carbide (SiC) super-junction (SJ) vertical diffusion metal-oxide-semiconductor (VDMOS). The employed simulation physics models were validated by the heavy-ion irradiation experiments of the commercially rated 1.2-kV SiC common VDMOS (C-VDMOS), which indicated a severe degeneration threshold of 500 V. The SiC common SJ VDMOS (C-SJ VDMOS) was proven to be sensitive to high-energy heavy-ion and represents comparative SEB performance compared with the SiC C-VDMOS. The robustness of the SiC SJ VDMOS with different single buffer layer (SBL) designs against a heavy-ion was simulated. It is found that the maximum temperature in the source metal/SiC interface and bottom of the structure could be compromised by the thickness of the buffer layer. As a result, the SiC SJ VDMOS with an optimal SBL exhibited a severe degeneration threshold of 800 V, which was a 60% increase compared to the SiC C-SJ VDMOS. [ABSTRACT FROM AUTHOR]

This brief presents 2-D numerical simulation results of a single-event burnout (SEB) in a 4H-silicon carbide (SiC) junction termination extension (JTE) termination structure of a power metal–oxide–semiconductor field-effect transistor (MOSFET). Using the rated 1.5-kV JTE termination structure, the most sensitive ion’s strike position to SEB is proved to be the edge of the P+/P− JTE region. Due to the severe punchthrough of the electric field, the source contact region is found to the most sensitive region to induce an SEB event. The SEB performance of the JTE termination structure with a single buffer layer or multilayer buffer is evaluated. The results show that the electric field distribution in four buffer layers (FBLs) is the most uniform to achieve the best SEB performance. Therefore, by adding an optimal FBL design to the termination region, the SEB threshold voltage can be increased to 1210 V instead of the common structure’s 250 V. The SEB safe operating area of the power MOSFET with an optimal FBL can increase more than three times compared with the common one. [ABSTRACT FROM AUTHOR]

In this article, a method of single-event burnout (SEB) hardening at high linear energy transfer (LET) value range is proposed and investigated by the 2-D numerical simulations. The improved MOSFET using this method and the conventional MOSFET are analyzed and compared to evaluate the effectiveness of this method. Simulation results show that, compared with the conventional MOSFET, the improved MOSFET using this method can effectively and quickly reduce the internal high electric field, thereby reducing the temperature. Under the condition of a LET value of 0.5 pC/μm and a drain voltage of 1200 V, the maximum drain current is 0.168 A, and the maximum global device temperature is 1724 K, which is much lower than the melting down temperature of silicon carbide (SiC) (3100 K). The hardening method in this article can be applied to different breakdown voltages by adjusting structure parameters. [ABSTRACT FROM AUTHOR]

In this article, the performance and triggering mechanism of the single-event burnout (SEB) of a 4H-SiC trench-gate (TG) MOSFET structure are evaluated by the 2-D numerical simulations. The novel N+ island buffer 4H-SiC TG MOSFET and the conventional TG 4H-SiC MOSFET are analyzed and compared to examine whether an N+ island region introduced in the second buffer can effectively reduce the impact ionization located at the N− drift/N+ buffer junction and improve device tolerance to the SEB. The TCAD simulation results revealed that compared with the conventional structure, which is a simple double-buffer structure, the N+ island buffer-hardened structure changed the burnout threshold voltage, improving the SEB performance significantly. In addition, the results proved that the impact ionization played an important role in the SEB triggering mechanism, significantly affecting the SEB performance of the 4H-SiC TG MOSFET. The performance of the hardened N+ island buffer with a different dopant concentration of N-buffer 2 and a size of N+ island is discussed. The specific burnout threshold voltage at the optimal parameters of the proposed structure is 47% higher than that of the conventional structure. [ABSTRACT FROM AUTHOR]

In this paper, using the charge-plasma concept, we propose an effective technique to implement a graded channel (GC) nanoscale MOSFET without the need for a separate implantation. The characteristics are demonstrated and compared with conventional dopingless, junctionless, and underlap inversion-mode MOSFET. The results show that the proposed GC device exhibits reduced drain-induced barrier lowering, improved intrinsic gain ( A V ), cutoff frequency ( f T ), and maximum oscillation frequency ( f \mathrm{MAX} ). Our approach overcomes the difficulty of creating a narrow GC doping profile and, thus, makes the GC MOSFET more attractive in carrying on with the scaling trend. The possible fabrication process flow of GC-double-gate (DG) FET is also proposed. [ABSTRACT FROM AUTHOR]