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We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around Si nanowires with diameters in the range from 4 nm to 8 nm with gate length from 8 nm to 14 nm. We studied the output and transfer characteristics, interpreting the behavior in the sub-threshold region and in the ON state in terms of the spatial charge distribution and the mobility computed with the same simulator. We analyzed the results, highlighting the contribution of different valleys and subbands and the effect of the gate bias on the energy and velocity profiles. Finally the scaling behavior was studied, showing that only the devices with D = 4 nm maintain a good control of the short channel effects down to the gate length of 8 nm . [ABSTRACT FROM AUTHOR]

Abstract: This work presents a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin SOI devices (ET-FDSOI, also known as UTSOI) to sub-32nm nodes using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on Short Channel Effects (SCEs). Simulations show that for channel lengths shorter than 20nm, silicon thickness thinner than 5nm are needed to control Drain Induced Barrier Lowering (DIBL) below 100mV/V. However, thickness variability and mobility reduction could play an important role for so small thickness. Nevertheless, we show that with the appropriate combination of UTBOX and GP it is possible to use thicker Si layers, even for channels shorter than 20nm, and keeping SCEs under control, i.e., DIBL below 100mV/V. [Copyright &y& Elsevier]

Abstract: With the 32nm node in mass production, simulation tools have to include quantum effects to correctly describe the behavior of the devices. The Multi-Subband Ensemble Monte Carlo (MSB-EMC) approach constitutes today’s most accurate method for the study of nanodevices with important applications to SOI devices. However, the study of bulk devices with MSB-EMC codes presents practical limitations arising from the device geometry and the existence of a semi-infinite quantum well. This work presents a in-depth study of such issues to properly apply the Multi-Subband approach to bulk devices. The developed simulator has been used to study bulk-nMOSFETs for the 32nm technological node and beyond which still constitutes the mainstream technology in commercial ICs and to compare them to their SOI counterparts. [Copyright &y& Elsevier]

Abstract: State-of-the-Art devices in mass production are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Multi-gate devices based on SOI technology, are one of the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials and substrate orientations to enhance the performance of CMOS circuits. This paper studies the electron transport in DGSOI devices with aggressive scaling and the role of different confinement and transport directions in the characteristics of next generation devices using a Multi-Subband Ensemble Monte Carlo simulator (MSB-EMC). Our simulations show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed. [Copyright &y& Elsevier]

We show the importance of acoustic phonon confinement in ultrathin silicon-on-insulator inversion layers by comparing electron mobility calculated by the Monte Carlo method assuming a bulk acoustic phonon model (the usual procedure) with that obtained by using a confined acoustic phonon model developed in this work. Both freestanding and rigid boundary conditions are taken into account for the evaluation of the confined phonon dispersion in a three-layer structure. Mobility reductions of 30% are observed for silicon thicknesses of around 5–10 nm when the confined acoustic phonon model is used. [ABSTRACT FROM AUTHOR]

We used an ensemble Monte Carlo simulator to study both the dc and transient behavior of a double gate silicon-on-insulator transistor (DGSOI) operated as a velocity modulation transistor (VMT) and as a conventional field effect transistor (FET). Operated as a VMT, the DGSOI transistor provides switching times shorter than 1 ps regardless of the channel length, with a significant current modulation factor at room temperature. The same device operated as a FET provides much longer switching times which, in addition, increase with the channel length. [ABSTRACT FROM AUTHOR]