Search

We report a new curing procedure of a plasma enhanced chemical vapor deposited SiCOH glasses for interlayer dielectric applications in microelectronic. It is demonstrated that SiOCH glasses with improved mechanical properties and ultralow dielectric constant can be obtained by controlled decomposition of the porogen molecules used to create nanoscale pores, prior to the UV-hardening step. The Young’s modulus (YM) of conventional SiOCH-based glasses with 32% open porosity hardened with porogen is 4.6 GPa, this value is shown to increase up to 5.2 GPa with even 46% open porosity, when the glasses are hardened after porogen removal. This increase in porosity is accompanied by significant reduction in the dielectric constant from 2.3 to 1.8. The increased YM is related to an enhanced molecular-bridging mechanism when film is hardened without porogen that was explained on the base of percolation of rigidity theory and random network concepts. [ABSTRACT FROM AUTHOR]

The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO[sub 2] with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the characteristics and properties of low-k dielectrics. In addition it addresses some of the needs for improved metrology for determining pore sizes, size distributions, structure, and mechanical properties. © 2003 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Performance improvements in microelectronic integrated circuits (ICs) over the past few decades have, for the most part, been achieved by increasing transistor speed, reducing transistor size, and packing more transistors onto a single chip. Smaller transistors work faster, so ICs have become faster and more complex. An emerging factor that may disrupt this trend is the slowing speed of signal propagation within the chip. Signal delays, caused by the interconnection wiring, increase with each generation of scaling and may soon limit the overall performance of the integrated system. [Copyright &y& Elsevier]

Abstract: This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125nm height which is used as a fin and a sloped bottom of 200nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional α-C hard mask of 90nm (with antireflective SiOC coating of 35nm) on top of the STI stack (70nm nitride on top of 8nm oxide). The nitride layer and the top straight part of the fin is patterned using CH2F2/SF6/N2 chemistry and α-C as a mask, while the bottom sloped part is patterned using Cl2/O2/N2 chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged. [Copyright &y& Elsevier]