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Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) are regarded as the key device for the next generation of power electronics. However, wide applications are hindered by the threshold voltage instability. How the threshold voltage drifts under both static and dynamic gate stress has been reported. But the underpinning mechanism remains to be revealed, which is the basis of the exploration of the application solutions. This letter is to investigate why the threshold voltage drifts. It is found that the local electric field plays the key role behind the threshold instability, which is a function of dVGS/dt. Based on that, a physical model is proposed and experimentally verified. These findings provide not only a way to understand the mechanism but also a hint of how to mitigate the threshold instability by active gating in power electronics applications. [ABSTRACT FROM AUTHOR]

Parallel devices in nonuniform conditions can easily lead to reduced overall reliability or even failure due to uneven energy distribution. Especially under long-term avalanche stresses, the degradation of the device may have a great impact on the electrical parameters and performance. To study the degradation tendency and aging mechanism of parallel-connected silicon carbide (SiC) MOSFET, the repetitive unclamped inductive switching (UIS) experiments are carried out in this article. Technology computer-aided design (TCAD) simulations are utilized to simulate the temperature change and current distribution of the chip during an avalanche. The results showed that for planar and trench devices, the electrical parameters drifts are different during repetitive avalanches. The degradation rates are unequal for parallel devices with different case temperatures. Two degradation mechanisms, including hot holes injection and trapping in the gate oxide and metal aging, are found to dominate in the repetitive avalanche process. The findings are helpful for better understanding of degradations for parallel repetitive avalanches in device applications. [ABSTRACT FROM AUTHOR]

With increasing applications of silicon carbide power MOSFETs, more attention is being paid to reliability issues, among which the long-term stability of the gate threshold voltage is of paramount importance. In this article, laboratory experiments are conducted to investigate the threshold voltage instability under ac gate stresses with different duty ratios, and on and off-state gate voltages. It is found that no prominent drift would occur even for bipolar gate stresses, as long as the off-state gate voltage is within (higher than) the critical negative bias voltage which is related to the device fabrication process. Furthermore, not only the gate voltage swing but also the gate voltage polarity will affect the speed of threshold voltage drift when it occurs. The findings are intended for better understanding and management of potential threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]

For silicon carbide (SiC) power MOSFETs, threshold voltage drift is a remaining obstacle in their way to the market. This study experimentally investigates the drift under dynamic or switching gate stresses. It is shown that, beside static stress, the switching events can themselves be a driving force of the threshold voltage drift. However, this happens only when the dynamic gate stress is bipolar. The study extends to show that the dynamic stress induced drift can be sustained. The findings can be used in further work for managing and coping with the threshold voltage drift in device applications. [ABSTRACT FROM AUTHOR]