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In this paper, we present a theory of electron mobility in nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs). Numerical approach consists of the Kubo-Greenwood formula and the self-consistent solution of the Schrödinger and Poisson equations for cylindrical gated nanowires. Phonons and surface roughness scatterings are treated in accordance with literature. Moreover, this paper focuses on nanowire MOSFETs using a high-k/metal gate stack. This configuration is chosen to be as close as possible to experimental investigations. The impact of trapped charges in the oxide, called remote Coulomb scattering, is modeled following the Kubo-Greenwood approach and accounting for screening effect. A comparison with experiment is performed for a single cylindrical nanowire with diameter of 20 nm. The diameter dependence is highlighted and it is shown that silicon thickness has a great impact on the mobility for diameters below 10 nm. [ABSTRACT FROM AUTHOR]

The Junctionless Double-Gate MOSFET combined with a Dual-Material Gate (JL-DMDG) is interesting for future ultra-scaled devices thanks to a simplified technological process (no junctions), reduced leakage currents and capability to reduce short-channel effects and hot-carrier effects (due to the step in the potential profile induced by the dual-material gate). In this work, we investigate the bipolar amplification and charge collection in JL-DMDG submitted to heavy-ion irradiation. The impact on single-event transients of several parameters such as the length of the high-workfunction gate-material region and of the workfunction of the low-workfunction gate-material region is also particularly addressed. We show that JL-DMDG is more sensitive to radiation than more conventional devices with single-material-gate or operating in inversion-mode. [ABSTRACT FROM AUTHOR]

Dual-material double-gate (DMDG) structure is a promising structure for future ultra-scaled devices thanks to its capability to reduce short channel effects (SCEs) and hot-carrier induced effects (HCEs). This is due to a step in the surface-potential profile which screens the source side of the channel from drain-potential variations and reduces the drain electric field. In this work, we investigate the DMDG sensitivity to single-event transients. The impact of dual gate material workfunctions on the bipolar gain is particularly addressed. We show that DMDG is naturally less radiation immune than the usual single-material DG (SMDG) devices. [ABSTRACT FROM AUTHOR]

The Junctionless (JL) Single-Gate SOI (JL-SOI) technology is potentially interesting for future ultra-scaled devices, due to a simplified technological process and reduced leakage currents. In this work, we investigate the radiation sensitivity of JL-SOI MOSFETs and 6 T SRAM cells. A detailed comparison with JL Double-Gate (JL-DG), inversion-mode (IM) SOI (IM-SOI), and IM-DG MOSFETs has been performed. 3-D simulations indicate that JL-SOI MOSFETs and SRAM cells are naturally less immune to radiation than the other structures. [ABSTRACT FROM AUTHOR]

Abstract: We developed a quantum–mechanical simulation code to study subthreshold performances and carrier quantum confinement in double-gate MOSFETs with high-mobility channel materials like Ge and III–V semiconductors. The code is based on the two-dimensional and self-consistent numerical solving of Poisson and Schrödinger equations coupled with the drift–diffusion transport equation. We systematically evaluate and analyze drain-induced barrier lowering and carrier quantum confinement in Si, Ge, In0.53Ga0.47As and GaAs based double-gate devices. Results show that SCEs in In0.53Ga0.47As and GaAs devices are lower than in Si and Ge counterparts. However, when the channel film thickness is reduced, carrier confinement is found to strongly impact double-gate device operation with high-mobility materials owing to their low confinement effective mass in the lowest energy valley. [Copyright &y& Elsevier]

In this paper, we present a compact model of double-gate MOSFET architecture including ballistic and quasi-ballistic transport down to 20 nm channel length. In addition, this original model takes into account short-channel effects (SCE/DIBL) by a simple analytical approach. The quasi-ballistic transport description is based on Lundstrom's backscattering coefficient given by the so-called flux method. We also include an original description of scattering of processes by introducing the 'dynamical mean free path' formalism. Moreover, we implemented our model in a Verilog-A environment, and applied it to the simulation of circuit elements such as CMOS inverters and ring oscillators to analyse the impact of ballistic/quasi-ballistic transport on circuit performances. Finally, in order to validate our work, we confronted this model with numerical simulation of CMOS and ring oscillator in ballistic case. [ABSTRACT FROM AUTHOR]

Abstract: This study analyzes by 2-D numerical simulation the electrical performances of independent double-gate (IDG) MOSFET with high-permittivity (high-κ) dielectric gate stacks. We particularly address the operation of elementary devices as well as of the associated CMOS inverters, which are investigated in terms of static power dissipation and delay. We show that the introduction of a pure high-κ gate dielectric layer degrades the device immunity to short-channel effects and the power consumption of the CMOS inverter, but simultaneously improves the inverter speed, with respect to performances of a reference transistor with a SiO2 gate oxide with the same equivalent oxide thickness. However, in real devices, the existence of a native oxide between the high-κ gate dielectric and the underlying semiconductor reduces parasitic electrostatic effects and sensibly improves inverter speed and power consumption. A detailed comparison between the operation of high-κ gate stack-based double-gate devices with independent and connected gates is also presented. [Copyright &y& Elsevier]

We present an analytical model for the subthreshold characteristic of ultra-thin independent double-gate (IDG) MOSFETs working in the ballistic regime. This model takes into account short-channel effects, quantisation effects and source-to-drain tunnelling (Wentzel-Kramers-Brillouin (WKB) approximation) in the expression of the subthreshold drain current. Important device parameters, such as off-state current or subthreshold swing, can be easily evaluated through this full analytical approach. The model can be successfully implemented in a Technologies Computer-Aided Design (TCAD) circuit simulator for the simulation of IDG MOSFET-based circuits. [ABSTRACT FROM AUTHOR]

The impact of quantum confinement effects on the transient response of 32 nm Multiple-Gate nanowire MOSFETs to heavy ion irradiation is investigated using 3D quantum numerical simulation. The drain current transient induced by an ion strike and the bipolar amplification of Double-Gate, Triple-Gate, Omega-Gate and Gate-All-Around architectures is simulated for the 2007, 2009 and 2011 ITRS Low Power technology nodes. The consequences of quantum-mechanical confinement on single-event transient immunity when devices are scaled down to 20 nm gate length and 5 nm thick silicon channel are then analyzed. [ABSTRACT FROM AUTHOR]

A compact model for the drain current and node charges in symmetrical Double-Gate (DG) MOSFET, including short-channel and carrier confinement effects is developed. The model is particularly well adapted to ultra-scaled devices, with short-channel lengths and ultra-thin silicon films. An extensive comparison step with 2D quantum numerical simulation fully validates the model. The model is also shown to reproduce with an excellent accuracy experimental drain current measured in DG devices fabricated with Silicon-on-Nothing (SON) process. Finally, the DG model has been successfully implemented in Eldo IC analog simulator, demonstrating the application of the model to circuit simulation. [ABSTRACT FROM AUTHOR]

The response to single-event transient of decananometer SOI MOSFETs is investigated by heavy ion experiment and by 3D quantum simulation. The 50 nm FD Single-Gate SOI devices have been irradiated with heavy ions at GANIL (Caen, France) using a new experimental setup. Three-dimensional numerical simulation is used to get further insights and to extrapolate the experimental results when devices are scaled down. For ultra-thin films new phenomena such as quantum-mechanical confinement have to be carefully considered in the device simulation. These effects are found to have an increasing impact on the operation of future ultra-thin single- and double-gate devices submitted to heavy ion irradiation. [ABSTRACT FROM AUTHOR]

The sensitivity to heavy ions of three 45-nm multi-gate transistors is evaluated by 3-D simulation. An in depth investigation of main internal parameters is performed to study the electrical response of the different device architectures under irradiation. The obtained results are in agreement with the electrical behavior trends of these devices. [ABSTRACT FROM AUTHOR]

A compact model for the threshold voltage in Double-Gate (DG) MOSFET is developed. The model takes into account short-channel effects, carrier quantization and temperature dependence of the threshold voltage. We assume a parabolic variation of the potential with the vertical position in the silicon film at threshold. An analytical expression for the surface potential dependence as a function of bias and position in the silicon film is also developed and used for the inversion charge calculation. The model has been fully validated by 2D quantum numerical simulation and is used to predict the threshold voltage roll-off in DG MOSFET with very short channel lengths and thin films. The comparison with measured threshold voltages shows that the model reproduces with an excellent accuracy the experimental data. [ABSTRACT FROM AUTHOR]

A quantum-mechanical compact model of the threshold voltage ( V T ) for quantum nanowire MOSFETs has been developed. This approach is based on analytical solutions for the decoupled 2D Schrödinger and 1D Poisson equations solved in the silicon channel. A quantum correction based on the perturbation theory has been also introduced to improve the model accuracy. Finally, the validity of the model has been verified by comparison with data obtained with a 2D/3D Poisson-Schrödinger drift-diffusion simulation code. [ABSTRACT FROM AUTHOR]

Abstract: In this work, the degradation of electrical performances of Double-Gate MOSFET due to the fringing induced barrier lowering (FIBL) effect induced by high-κ gate dielectrics is investigated using a two-dimensional quantum-mechanical simulation code. Our numerical results show that all electrical parameters, such as the threshold voltage (V T), device immunity to short-channel effects, off-state current (I off), and subthreshold slope (S) are degraded when κ increases (3.9< κ <100). This degradation is both function of the channel length and the gate dielectric stack composition (number of layers, κ value). In particular, it is shown that the introduction of a thin (<1nm thick) interfacial oxide layer can reduce or even completely suppress the FIBL for a given equivalent oxide thickness of the gate dielectric stack. [Copyright &y& Elsevier]

A new 2-D simulation code resolving the Schro¨dinger and Poisson equations coupled with the ballistic transport equation in double-gate (DG) devices has been developed. The present approach also includes the quantum mechanical tunneling of carriers through the source-to-drain barrier and the wave-function penetration in the gate oxide. This code has been used to investigate the operation of DG metal–oxide–semiconductor field-effect transistors (MOSFETs) in the deca-nanometer range (5–20 nm) with ultra-thin gate oxide and film bodies (1.5 nm). The present study highlights the impact of quantum tunneling on the DG MOSFET scaling by particularly analyzing several critical performance indicators such as short-channel effects, off-state current and subthreshold slope. [Copyright &y& Elsevier]

A new 2-D simulation code resolving the Schro¨dinger and Poisson equations coupled with the ballistic transport equation in double-gate (DG) devices has been developed. The present approach also includes the quantum mechanical tunneling of carriers through the source-to-drain barrier and the wave function penetration in the gate oxide. This code has been used to investigate the operation of DG SOI MOSFETs in the deca–nanometer range (5–20 nm) with ultra-thin gate oxide and film bodies (1.5 nm). The present study particularly emphasizes on the impact of quantum tunneling on the DG SOI MOSFET scaling in terms of short-channel effects, off-state current and subthreshold slope. [Copyright &y& Elsevier]

The aim of this work is to investigate non-stationary transport effects occurring in 50 nm MOSFET technology and to provide guidelines for technology optimization in order to maximize the impact of these effects on device performances. We analyze quantitatively the real impact of technology on the needed level of accuracy for carrier transport modeling and we show which recipes must be used to evaluate the performances of advanced device architectures. The original point of this work is the investigation of technology influence on injection velocity at source side and on drain current. The results open the perspective of specific engineering of access regions in order to take full advantage of non-stationary effects on the drain current. [Copyright &y& Elsevier]

In this work, we present an atomic-scale modeling of a single conduction channel double-gate MOSFET based on the self-consistent solving of the two-dimensional Poisson equation with the Schro¨dinger equation. This later, expressed in tight-binding, is solved using the Green’s function formalism in the axial part of the device (i.e. the source–channel–drain region) modeled as a single atomic linear chain and sandwiched between two gate dielectrics treated as perfect insulating media. For device with channel length typically below 10 nm, our results show that source-to-drain tunneling effect and electron reflection in the channel severely impact the device characteristics. Nevertheless, essential field-effect transistor behaviors are preserved, which demonstrates that the operation of double-gate devices can be still considered even at this ultimate limit of a single conduction channel depicted at the atomic-scale. [Copyright &y& Elsevier]

Abstract: With the constant reduction of the transistor dimensions, new transport mechanisms in the conduction channels must be taken into account, as the quasi-ballistic transport. To realize how close to the ballistic limit a nanoFET operates, calculating the ratio of the mean-free-path to the critical length at the top of the source-to-channel barrier becomes an interesting investigation. After an introduction concerning the ballistic transport into the current devices, we will present the electrically characterized architectures and the methodology used to extract the backscattering coefficient (r SAT) for different gate lengths (10, 20 and 70nm) and with temperatures ranging from 100K to 290K. We found that although the gate length is very small, the Double-Gate MOSFETs (DGMOSFETs) are not so close to the ballistic frontier (r SAT =0). [Copyright &y& Elsevier]

Abstract: This work investigates the conduction band structure of silicon nanowires, its dependence with the wire width and its influences on the electrical performances of Si nanowire-based MOSFET’s working in the ballistic regime. The energy dispersions relations for Si nanowires have been calculated using a sp3 tight-binding model and the ballistic response of n-channel devices with a 3D Poisson–Schrödinger solver considering a mode-space approach and open boundary conditions (NEGF formalism). Results are compared with data obtained considering the parabolic bulk effective mass approximation, highlighting in this last case the overestimation of the I on current, up to 60% for the smallest (1.36nm×1.36nm Si wire) devices. [Copyright &y& Elsevier]