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Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal–oxide–semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to form steep p-type channel profiles in n-channel MOS field-effect transistors (nMOSFETs) due to extremely low diffusivity of boron and indium in Si:C layers. This structure with low channel impurity improves mobility and suppresses threshold voltage (VTH) variation. Both items are essential for aggressively scaled MOSFETs with a gate length less than 25 nm. We demonstrated well-controlled, high-performance, and low VTH variability nMOSFETs with a Si:C-Si epitaxial channel structure. [ABSTRACT FROM PUBLISHER]

Abstract: Embedded silicon carbon alloy (e-Si:C) technology for source and drain (S/D) is expected to improve nMOSFET drive current. The distribution and activation characteristics of arsenic in Si:C film and the interfacial solid-phase reaction of the Ni/Si:C system were studied with the aim of achieving the maximum improvement of the characteristics of e-Si:C S/D. It was clarified that the active carrier concentration of Si:C decreased with increasing carbon concentration compared to the control Si. There is concern that the low doping activation in Si:C increases series resistance of e-Si:C S/D nMOSFETs and degrades the performance gain expected from the strain effect. [Copyright &y& Elsevier]

Abstract: In general, closer proximity of embedded SiGe (eSiGe) source drain (S/D) structure to the channel improves p-channel metal oxide semiconductor field-effect transistor (pMOSFET) performance because of the higher stress in the channel. However, we found the critical optimization methodology which has a relation between boron diffusion modulation in SiGe and short channel effect (SCE) in the context of the eSiGe proximity change. Therefore, additional source drain extension (SDE) optimization is required to improve device performance with closer eSiGe proximity focusing on the parasitic resistance reduction. As a result of the optimization, we have demonstrated high drive current of 755μA/μm at V dd =1.0V, I OFF =100nA/μm, 30nm gate length pMOSFET. [Copyright &y& Elsevier]