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A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a two-dimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 ‘wings,’ where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility. [ABSTRACT FROM AUTHOR]

The transport properties of holes in Si, Ge, and Si1-xGex under high compressive stresses are studied with a Monte Carlo simulation method. Stress significantly improves the low-energy mass and mobility, while its effect is diminished in the high-energy bandstructure. The transient behavior of the carrier velocity exhibits a double-overshoot peak at high driving field. This double-overshoot behavior is manifested in carrier-velocity profiles in simulated short-channel PMOS devices. In steady state at lower field, the hole velocity exceeds the saturation velocity at high field. This leads to a negative differential resistance effect in simulated resistors. We propose to use this effect, generic to cubic semiconductors, for transferred-hole devices. An advantage of this approach is that it can be integrated into the conventional stress-engineered Si or Ge logic process. [ABSTRACT FROM AUTHOR]