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This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225 °C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed. [ABSTRACT FROM AUTHOR]

Abstract: In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects. [Copyright &y& Elsevier]

Abstract: This paper analyzes the influence of negative charges (NC) located at the gate edges on the advanced MOSFETs behavior, paying particular attention to the subthreshold slope, S, maximum transconductance, Gm max, and analog figures of merit, such as transconductance over drain current ratio, Gm /ID , output conductance, GD , Early voltage, V EA, and intrinsic gain. General trends obtained by two-dimensional numerical simulations on double-gate (DG) structures are whenever possible qualitatively correlated with experimental data obtained on FinFETs. We show that the presence of negative charges at the gate edges while degrading the subthreshold behavior and analog figures of merit (especially for long-channel devices) can result in apparent improved control of short-channel effects and higher Gm max. The origin of such twofold impact of negative charges at the gate edges on the device behavior is also analyzed by 2-D device simulations and a simplified two-transistors model. [Copyright &y& Elsevier]