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In‐memory computing using memristor‐based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high‐energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module‐enable signal and input‐checker bits. [ABSTRACT FROM AUTHOR]

A computing scheme that can solve complex tasks is necessary as the big data field proliferates. Probabilistic computing (p-computing) paves the way to efficiently handle problems based on stochastic units called probabilistic bits (p-bits). This study proposes p-computing based on the threshold switching (TS) behavior of a Cu0.1Te0.9/HfO2/Pt (CTHP) diffusive memristor. The theoretical background of the p-computing resembling the Hopfield network structure is introduced to explain the p-computing system. P-bits are realized by the stochastic TS behavior of CTHP diffusive memristors, and they are connected to form the p-computing network. The memristor-based p-bit is likely to be '0' and '1', of which probability is controlled by an input voltage. The memristor-based p-computing enables all 16 Boolean logic operations in both forward and inverted operations, showing the possibility of expanding its uses for complex operations, such as full adder and factorization. Designing a computing scheme to solve complex tasks as the big data field proliferates remains a challenge. Here, the authors present a probabilistic bit generation hardware built using the random nature of CuxTe1−x/HfO2/Pt memristors capable of performing logic gates with invertible mode, showing the expandability to complex logic circuits. [ABSTRACT FROM AUTHOR]

Neuromorphic engineering aims to mimic brain functions to achieve energy‐efficient artificial intelligence. Since researchers have indicated that memristors can mimic synapses and neurons, various studies have demonstrated the operation of neural networks using memristive dot product engine (MDPE) hardware. However, although several feasible implementations of synapse and neuron behaviors have been reported, few studies have demonstrated the system‐level energy‐efficient operation on the hardware. This work proposes a novel system inspired by the neuromodulation of the brain, referred to as a "stashing system." In the system, the trained synapses are stashed temporarily during the training of the spiking neural network and then merged for inferencing. The software simulation first confirmed the working principle of the stashing system. Then, a hardware demonstration is performed at an integrated 32 × 32 MDPE embodying a self‐rectifying and electroforming‐free memristor cell to validate the system. The results confirm that energy consumption in the memristor array is reduced by 37% for the unsupervised learning of the MNIST dataset. [ABSTRACT FROM AUTHOR]

The development of memristor‐based stateful logic circuits can minimize data movement during the computing process to achieve in‐memory computing, mitigating the von Neumann bottleneck in the current computing architecture. Herein, a method to combine resistance–resistance (R–R) and voltage–resistance (V–R) logic gates to implement exclusive logic gates composed of APMR‐two‐2(XOR, IMP, RIMP) and APMR‐three‐4XOR, where APMR means antiparallel memristors with a series resistor, is suggested. The proposed gates can accelerate XOR logic operation in a single cycle and expand for the n‐bit input. The performance of the proposed logic gate is then demonstrated with a 1‐bit full adder–subtractor along with the comparison of an n‐bit ripple carry adder. It shows that the implementation for the n‐bit adder takes 4n+1 memristors within 2n+1 steps, which significantly improves the optimization in terms of space‐ and time‐related costs compared with other memristive logic gates. Subsequently, the improved adder circuit can be further utilized to implement an n‐bit multiplier. In addition, the evaluation of the device stress on the various logic gates confirms that the proposed logic gates are reliable. [ABSTRACT FROM AUTHOR]

Recent advances in physical reservoir computing, which is a type of temporal kernel, have made it possible to perform complicated timing-related tasks using a linear classifier. However, the fixed reservoir dynamics in previous studies have limited application fields. In this study, temporal kernel computing was implemented with a physical kernel that consisted of a W/HfO2/TiN memristor, a capacitor, and a resistor, in which the kernel dynamics could be arbitrarily controlled by changing the circuit parameters. After the capability of the temporal kernel to identify the static MNIST data was proven, the system was adopted to recognize the sequential data, ultrasound (malignancy of lesions) and electrocardiogram (arrhythmia), that had a significantly different time constant (10−7 vs. 1 s). The suggested system feasibly performed the tasks by simply varying the capacitance and resistance. These functionalities demonstrate the high adaptability of the present temporal kernel compared to the previous ones. Recently there has been an interest in utilising memristors as physical temporal kernels. Here, Jang et al demonstrate a physical temporal kernel using a memristor combined with a capacitor and resistor, where the additional circuit elements can be varied to allow the system to tackle a diverse range of tasks. [ABSTRACT FROM AUTHOR]

Combining Boolean logic and nonvolatile memory functions, memristor‐based stateful logic circuits can minimize data movement during the computing process to achieve futuristic in‐memory computing. This may solve the problem of the von Neumann bottleneck in the current computing architecture. Herein, the recent developments in memristor‐based stateful logic computation are discussed from several perspectives, including the device, circuit, operational principles, and applications. Stateful logic gates correspond to in‐memory logic gates, with the inputs and outputs having identical physical entities, such as resistance. The developments in stateful logic primitive gates reported in the past decade are summarized. The influential factors in their actual implementation for stateful logic computation are also discussed. Then, methods for allocating the logic gates into the crossbar array are explained, which are for implementing the complex computing instances in the crossbar array. Finally, several data‐intensive applications achieved using the in‐memory computing method are discussed for the practical application of stateful logic in future computing systems. [ABSTRACT FROM AUTHOR]

A true random‐number generator (TRNG) and a nonlinear feedback shift register (NFSR) are combined to create a new type of TRNG. This TRNG is based on the intrinsic stochasticity of threshold switching behavior in a Pt/HfO2/TiN memristor and an NFSR circuit. Considering the transition rate of the hopping process, the stochasticity of the delay time can be attributed to the phonon‐assisted hopping process. This novel TRNG passes all 15 National Institute of Standards and Technology randomness tests without post‐processing steps, proving its performance as a hardware security application. By combining the TRNG with the NFSR, the bit generation rate is further improved, allowing it to be used for high‐speed applications. [ABSTRACT FROM AUTHOR]

Memristor crossbar arrays were fabricated based on a Ti/HfO2/Ti stack that exhibited electroforming-free behavior and low device variability in a 10 x 10 array size. The binary states of high-resistance-state and low-resistance-state in the bipolar memristor device were used for the synaptic weight representation of a binarized neural network. The electroforming-free memristor was confirmed as being suitable as a binary synaptic device because of its higher device yield, lower variability, and less severe malfunction (for example, hard break-down) than the electroformed memristors based on a Ti/HfO2/Pt structure. The feasibly working binarized neural network adopting the electroforming-free binary memristors was demonstrated through simulation. [ABSTRACT FROM AUTHOR]

In this Review, memristors are examined from the frameworks of both von Neumann and neuromorphic computing architectures. For the former, a new logic computational process based on the material implication is discussed. It consists of several memristors which play roles of combined logic processor and memory, called stateful logic circuit. In this circuit configuration, the logic process flows primarily along a time dimension, whereas in current von Neumann computers it occurs along a spatial dimension. In the stateful logic computation scheme, the energy required for the data transfer between the logic and memory chips can be saved. The non‐volatile memory in this circuit also saves the energy required for the data refresh. Neuromorphic (cognitive) computing refers to a computing paradigm that mimics the human brain. Currently, the neuromorphic or cognitive computing mainly relies on the software emulation of several brain functionalities, such as image and voice recognition utilizing the recently highlighted deep learning algorithm. However, the human brain typically consumes ≈10–20 Watts for selected “human‐like” tasks, which can be currently mimicked by a supercomputer with power consumption of several tens of kilo‐ to megawatts. Therefore, hardware implementation of such brain functionality must be eventually sought for power‐efficient computation. Several fundamental ideas for utilizing the memristors and their recent progresses in these regards are reviewed. Finally, material and processing issues are dealt with, which is followed by the conclusion and outlook of the field. These technical improvements will substantially decrease the energy consumption for futuristic information technology. [ABSTRACT FROM AUTHOR]

To facilitate the development of memristive devices, it is essential to resolve the problem of non-uniformity in switching, which is caused by the random nature of the filamentary switching mechanism in many resistance switching memories based on transition metal oxide. In addition, device parameters such as low- and high-state resistance should be regulated as desired. These issues can be overcome if memristive devices have switching limits for both the low- and high-resistance states and if their resistance values are highly controllable. In this study, a method termed self-limited switching for uniformly regulating the values of both the low- and high-resistance states is suggested, and the circuit configuration required for the self-limited switching is established in a Ta2O5/TaO x memristive structure. A method of improving the uniformity of multi-level resistance states in this memristive system is also proposed. [ABSTRACT FROM AUTHOR]

The self‐rectifying memristor with a bilayer of trap‐rich HfO2 and insulating Ta2O5 oxide layers is considered one of the most promising candidates for the memristive crossbar array due to its superior switching performance, scalability with 3D stacking, and low operating power. However, the output current variation due to the electron detrapping from trap states can cause the failure of critical operations in neuromorphic applications. This work suggests two solutions to mitigate the switching variations and insufficient data retention time by embedding gold nanodots and modifying the bias voltage application methods for read, write, and erase operations in the crossbar array. The switching mechanism is studied by varying the embedded position of the gold nanodots across the thickness direction of the bilayered oxides, which helped to optimize device performance further. Combining the two solutions into the proposed self‐rectifying memristor enables a single device to have the 7‐possible, stable states by preventing interstate overlap and securing the retention. Consequently, the hardware neural network consisting of self‐rectifying memristors with gold nanodots with the modified bias voltage application methods demonstrates a high inference accuracy of 93.1% in MNIST handwritten digit classification, comparable to the software‐based accuracy of 93.4%, benefiting from the enhanced multi‐state uniformity. [ABSTRACT FROM AUTHOR]

Stateful logic provides an attractive device‐level solution in achieving in‐memory computation, which can solve the critical problem of the von Neumann bottleneck − "memory wall" − in the current computer architecture. Recently, fully functional stateful logic operations and cascading are reported using a TiOx‐based dual‐bit memristor. In that work, all the 16 Boolean logic functions are accomplished in a stateful dual‐bit memristor, which can be expanded to more complicated computational tasks. This logic scheme is much more compact compared with the current complementary semiconductor field effect transistors based logic, providing the system with great area efficiency as well as energy‐saving performance. In such stateful logic device, the logic flow (cascading) is made along the time dimension. Therefore, "time efficiency" is the critical factor for estimating its performance. In this paper, two methods, changing the logic coding scheme and configuring the parallel‐circuit morphology, are suggested to improve the time efficiency of the previous dual‐bit memristor‐based logic. By implementing the two methods, a full adder can be demonstrated with three dual‐bit memristors and 12 operation steps, which corresponds to a 55.6% improvement compared with the previous work. [ABSTRACT FROM AUTHOR]

A true random number generator (TRNG) based on the stochastic delay and relaxation times of the threshold switching (TS) behavior in a Pt/HfO2/TiN memristor is proposed. The stochasticities of this device are attributed to its electron trapping and detrapping processes. This electronic‐switching‐based memristor exhibits several advantages, such as low power consumption and high reliability. A new circuit is designed to improve the simplicity, miniaturization, and lifetime of TRNG. The bitstreams collected from this TRNG pass the National Institute of Standards and Technology randomness tests without postprocessing, verifying the feasibility of adopting the memristor in hardware security applications. The bit generation rate in this work is sufficient for encryption applications requiring low power and low speed. A true random number generator (TRNG) based on a threshold switching behavior in a Pt/HfO2/TiN (PHT) memristor is proposed. The PHT memristor has stochastic delay and relaxation times, which are attributed to electron trapping and detrapping processes. A new circuit is designed to reduce the circuit size and to further improve the TRNG lifetime. [ABSTRACT FROM AUTHOR]

A correction related to the article "Fully Functional Logic-In-Memory Operations Based on a Reconfigurable Finite-State Machine Using a Single Memristor," that was published in the previous issue is presented.

Memristor offers a promising logic‐in‐memory (LIM) functionality to achieve the futuristic in‐memory computing machine, which may solve the problem of the "von Neumann bottleneck" in the conventional computer architecture. A sequential logic concept is capable of achieving LIM based on the finite‐state machine (FSM) using a single bipolar (BRS) or complementary resistive switching (CRS) memristor, where 14 of the 16 two‐input Boolean logic functions (XOR and XNOR are missing) are mapped between the resistance state and the terminal voltages. In this paper, a new FSM‐LIM concept based on a reconfigurable finite‐state machine (RFSM logic) is proposed, which is experimentally confirmed by a diode‐integrated single unipolar memristor. The scope of application of the proposed concept is further extended to three other asymmetric resistive switching devices, demonstrating the universality of the RFSM logic. With the use of different voltage conditions to denote logic input "1," the function of FSM is reconfigured between the two state‐transition equations. Through the triggering of the two state‐transition equations alternatively, all the 16 Boolean logic functions can be achieved in three steps at most, without the assistance of reading operation. These correspond to the logical completeness and nonvolatility. A logic concept based on a reconfigurable finite‐state machine (RFSM) using a single memristor is proposed. The RFSM logic uses the terminal voltages and the resistance of memristor to denote the logic inputs and output, respectively, enabling logic completeness and nonvolatility to be accomplished simultaneously. This feature implies an innovative strategy to achieve in‐memory computing. [ABSTRACT FROM AUTHOR]

A tri-stable memristive switching was demonstrated on a Pt/TiO2/Pt device and its underlying mechanism was suggested through a series of electrical measurements. Tri-stable switching could be initiated from a device in unipolar reset status. The unipolar reset status was obtained by performing an electroforming step on a pristine cell which was then followed by unipolar reset switching. It was postulated that tri-stable switching occurred at the location where the conductive filament (initially formed by the electroforming step) was ruptured by a subsequent unipolar reset process. The mechanism of the tri-stable memristive switching presented in this article was attributed to the migration of oxygen ions through the ruptured filament region and the resulting modulation of the Schottky-like interfaces. The assertion was further supported by a comparison study performed on a Pt/TiO2/TiO2−x/Pt cell. [ABSTRACT FROM AUTHOR]