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In-memory computing based on memristive logic is considered as a prospective non von Neumann computing paradigm. In this letter, we systematically analyze the four-variable logic method and map it into the operation of two anti-serial complementary memristors in the crossbar array architecture. Arbitrary Boolean logic can be implemented within three cycles with the experimental evidence of reconfigurable NAND, NOR, and XOR logic using Pt/HfO2/TiN devices. Taking advantage of the functional flexibility, a parallel 1-bit full adder that can be realized in 8 cycles within a $\textsf {4}\times \textsf {3}$ array has been designed and verified in simulation.

Brain-inspired computing is an emerging field, which intends to extend the capabilities of information technology beyond digital logic. The progress of the field relies on artificial synaptic devices as the building block for brainlike computing systems. Here, we report an electronic synapse based on a ferroelectric tunnel memristor, where its synaptic plasticity learning property can be controlled by nanoscale interface engineering. The effect of the interface engineering on the device performance was studied. Different memristor interfaces lead to an opposite virgin resistance state of the devices. More importantly, nanoscale interface engineering could tune the intrinsic band alignment of the ferroelectric/metal-semiconductor heterostructure over a large range of 1.28 eV, which eventually results in different memristive and spike-timing-dependent plasticity (STDP) properties of the devices. Bidirectional and unidirectional gradual resistance modulation of the devices could therefore be controlled by tuning the band alignment. This study gives useful insights on tuning device functionalities through nanoscale interface engineering. The diverse STDP forms of the memristors with different interfaces may play different specific roles in various spike neural networks.

Owing to the capability of integrating the information storage and computing in the same physical location, in-memory computing with memristors has become a research hotspot as a promising route for non von Neumann architecture. However, it is still a challenge to develop high performance devices as well as optimized logic methodologies to realize energy-efficient computing. Herein, filamentary Cu/GeTe/TiN memristor is reported to show satisfactory properties with nanosecond switching speed ( 104 cycles) and good retention (>104 s @85 °C). It is revealed that the charge carrier conduction mechanisms in high resistance and low resistance states are Schottky emission and hopping transport between the adjacent Cu clusters, respectively, based on the analysis of current-voltage behaviors and resistance-temperature characteristics. An intuitive picture is given to describe the dynamic processes of resistive switching. Moreover, based on the basic material implication (IMP) logic circuit, we proposed a reconfigurable logic method and experimentally implemented IMP, NOT, OR, and COPY logic functions. Design of a one-bit full adder with reduction in computational sequences and its validation in simulation further demonstrate the potential practical application. The results provide important progress towards understanding of resistive switching mechanism and realization of energy-efficient in-memory computing architecture.

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2 × 4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture.

Memristors are attracting considerable interest for their prospective applications in nonvolatile memory, neuromorphic computing, and in-memory computing. However, the nature of resistance switching is still under debate, and current fluctuation in memristors is one of the critical concerns for stable performance. In this work, random telegraph noise (RTN) as the indication of current instabilities in distinct resistance states of the Pt/Ti/HfO2/W memristor is thoroughly investigated. Standard two-level digital-like RTN, multilevel current instabilities with non-correlation/correlation defects, and irreversible current transitions are observed and analyzed. The dependence of RTN on the resistance and read bias reveals that the current fluctuation depends strongly on the morphology and evolution of the conductive filament composed of oxygen vacancies. Our results link the current fluctuation behaviors to the evolution of the conductive filament and will guide continuous optimization of memristive devices.