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This paper provides a quantitative characterization of the smallest, i.e., lean, buffer capacity necessary and sufficient to attain a desired throughput in serial production lines with identical exponential machines. The development is carried out in terms of normalized buffer capacity and production line efficiency. The smallest normalized buffer capacity required to ensure the desired line efficiency is referred to as the Lean Level of Buffering (LLB). Exact formulas for the LLB in two- and three-machine lines are presented and an approximate expression for the LLB in lines with more than three machines is derived. Along with these analytical results, several qualitative insights into the nature of lean buffering in serial production lines are presented., 1. Introduction Production lines with unreliable machines usually contain in-process buffers intended to decouple the machines and thereby reduce their mutual interference due to breakdowns. In the modern manufacturing environment, [...]

We investigate the lattice-based array partitioning based on the theory of the Smith Normal Form and we present two elegant techniques for partitioning arrays in parallel DoAll loops for message-passing parallel machines: (1) DoAll loops with constant dependencies for communication-free partitioning: a general solution of all possible communication-free partitioning is derived where the dependencies among array references are described in constant distance vectors. (2) DoAll loops with non-constant dependencies for block-communication partitioning: the dependencies among array references are described in non-constant distance vectors. We derive the partitioning equations which allocate all remote data to a unique processor such that only one block-communication can obtain all the remote data for the computation. By using the Smith Normal Form decomposition, we are also able to verily, our partitioning results. KEY WORDS: Data partitioning; communication optimization; parallel loop; Smith-normal-form.

Reducing memory space requirement is important to many applications. For data-intensive applications, it may help avoid executing the program out-of-core. For high-performance computing, memory space reduction may improve the cache hit talc as well as performance. For embedded systems, it can reduce the memory requirement, the memory latency and the energy consumption. This paper investigates program transformations which a compiler can use to reduce the memory space required for storing program data. In particular, the paper Lists integer programming to model the problem of combining loop shifting. loop fusion and array contraction to minimize the data memory required to execute a collection of multi-level loop nests. The integer programming problem is then reduced to an equivalent network flow problem which can be solved in polynomial time. KEY WORDS: Compilers; optimization; graph theory; network flow problem.

We conducted two experiments using a modified version of the N-Back task. For younger adults, there was an abrupt increase in reaction time of about 250 ms in passing from N = 1 to N > 1, indicating a cost associated with switching of the focus of attention within working memory. Response time costs remained constant over the range N = 2 to N = 5. Accuracy declined steadily over the full range of N (Experiment 1). Focus switch costs did not interact with either working memory updating (Experiment 1), or global task switching (Experiment 2). There were no age differences in RT costs once general slowing was taken into account, but there was a larger focus-switch-related accuracy cost in older adults than in younger adults. No age sensitivity was found for either updating or global task switching. The results suggest (a) that focus switching is a cognitive primitive, distinct from task switching and updating, and (b) that focus switching shows a specific age-related deficit in the accuracy domain.

A group of older adults with good hearing and a group with mild-to-moderate hearing loss were tested for recall of the final three words heard in a running memory task. Near perfect recall of the final words of the three-word sets by both good- and poor-hearing participants allowed the inference that all three words had been correctly identified. Nevertheless, the poor-hearing group recalled significantly fewer of the nonfinal words than did the better hearing group. This was true even though both groups were matched for age, education, and verbal ability. Results were taken as support for an effortfulness hypothesis: the notion that the extra effort that a hearing-impaired listener must expend to achieve perceptual success comes at the cost of processing resources that might otherwise be available for encoding the speech content in memory.

In this correspondence, we develop an asymptotic theory for the correlations of wavelet coefficients of the discrete wavelet transform (DWT) for fractionally differenced processes. It provides a theoretical justification for the approximate decorrelation property of the DWT for fractionally differenced processes. In addition, it provides insights on how the length of the wavelet filter affects the within scale correlations and the between scale correlations differently; for within scale correlations, increasing the length of the wavelet filter increases the rate of decay as the two wavelet coefficients get further apart, while for between scale correlations, using a wavelet filter that is long enough can reduce the between scale correlations even for wavelet coefficients that are close together. Index Terms--Decorrelation, discrete wavelet transform (DWT), length of a wavelet filter, long memory processes.

The computer industry may be accustomed to rapid change, but in the mass storage end of the business recently, the rate of progress has accelerated to an unprecedented clip. Historically. […]

Chips that implement video compression standards such as MPEG, JPEG, and P*64 could make everything from video phones to video teleconferencing a reality. But are these 'designed-by-committee' solutions the best […]

Rapidly advancing technology has always been a fact of life for computer designers, especially those working on the system core. In comparison, mass storage issues once looked simple. Sure, there […]

It started in the mainframe world over 20 years ago. In the late 1960s, IBM was building central processors that could cycle faster than big core memory planes. The architects […]