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With the explosive growth in data volume, the I/O bottleneck has become an increasingly daunting challenge for big data analytics in the Cloud. Recent studies have shown that moderate to high data redundancy clearly exists in primary storage systems in the Cloud. Our experimental studies reveal that data redundancy exhibits a much higher level of intensity on the I/O path than that on disks due to relatively high temporal access locality associated with small I/O requests to redundant data. Moreover, directly applying data deduplication to primary storage systems in the Cloud will likely cause space contention in memory and data fragmentation on disks. Based on these observations, we propose a performance-oriented I/O deduplication, called POD, rather than a capacity-oriented I/O deduplication, exemplified by iDedup, to improve the I/O performance of primary storage systems in the Cloud without sacrificing capacity savings of the latter. POD takes a two-pronged approach to improving the performance of primary storage systems and minimizing performance overhead of deduplication, namely, a request-based selective deduplication technique, called Select-Dedupe, to alleviate the data fragmentation and an adaptive memory management scheme, called iCache, to ease the memory contention between the bursty read traffic and the bursty write traffic. We have implemented a prototype of POD as a module in the Linux operating system. The experiments conducted on our lightweight prototype implementation of POD show that POD significantly outperforms iDedup in the I/O performance measure by up to 87.9 percent with an average of 58.8 percent. Moreover, our evaluation results also show that POD achieves comparable or better capacity savings than iDedup. [ABSTRACT FROM PUBLISHER]

This paper provides a quantitative characterization of the smallest, i.e., lean, buffer capacity necessary and sufficient to attain a desired throughput in serial production lines with identical exponential machines. The development is carried out in terms of normalized buffer capacity and production line efficiency. The smallest normalized buffer capacity required to ensure the desired line efficiency is referred to as the Lean Level of Buffering (LLB). Exact formulas for the LLB in two- and three-machine lines are presented and an approximate expression for the LLB in lines with more than three machines is derived. Along with these analytical results, several qualitative insights into the nature of lean buffering in serial production lines are presented., 1. Introduction Production lines with unreliable machines usually contain in-process buffers intended to decouple the machines and thereby reduce their mutual interference due to breakdowns. In the modern manufacturing environment, [...]

We investigate the lattice-based array partitioning based on the theory of the Smith Normal Form and we present two elegant techniques for partitioning arrays in parallel DoAll loops for message-passing parallel machines: (1) DoAll loops with constant dependencies for communication-free partitioning: a general solution of all possible communication-free partitioning is derived where the dependencies among array references are described in constant distance vectors. (2) DoAll loops with non-constant dependencies for block-communication partitioning: the dependencies among array references are described in non-constant distance vectors. We derive the partitioning equations which allocate all remote data to a unique processor such that only one block-communication can obtain all the remote data for the computation. By using the Smith Normal Form decomposition, we are also able to verily, our partitioning results. KEY WORDS: Data partitioning; communication optimization; parallel loop; Smith-normal-form.

Reducing memory space requirement is important to many applications. For data-intensive applications, it may help avoid executing the program out-of-core. For high-performance computing, memory space reduction may improve the cache hit talc as well as performance. For embedded systems, it can reduce the memory requirement, the memory latency and the energy consumption. This paper investigates program transformations which a compiler can use to reduce the memory space required for storing program data. In particular, the paper Lists integer programming to model the problem of combining loop shifting. loop fusion and array contraction to minimize the data memory required to execute a collection of multi-level loop nests. The integer programming problem is then reduced to an equivalent network flow problem which can be solved in polynomial time. KEY WORDS: Compilers; optimization; graph theory; network flow problem.

We conducted two experiments using a modified version of the N-Back task. For younger adults, there was an abrupt increase in reaction time of about 250 ms in passing from N = 1 to N > 1, indicating a cost associated with switching of the focus of attention within working memory. Response time costs remained constant over the range N = 2 to N = 5. Accuracy declined steadily over the full range of N (Experiment 1). Focus switch costs did not interact with either working memory updating (Experiment 1), or global task switching (Experiment 2). There were no age differences in RT costs once general slowing was taken into account, but there was a larger focus-switch-related accuracy cost in older adults than in younger adults. No age sensitivity was found for either updating or global task switching. The results suggest (a) that focus switching is a cognitive primitive, distinct from task switching and updating, and (b) that focus switching shows a specific age-related deficit in the accuracy domain.

A group of older adults with good hearing and a group with mild-to-moderate hearing loss were tested for recall of the final three words heard in a running memory task. Near perfect recall of the final words of the three-word sets by both good- and poor-hearing participants allowed the inference that all three words had been correctly identified. Nevertheless, the poor-hearing group recalled significantly fewer of the nonfinal words than did the better hearing group. This was true even though both groups were matched for age, education, and verbal ability. Results were taken as support for an effortfulness hypothesis: the notion that the extra effort that a hearing-impaired listener must expend to achieve perceptual success comes at the cost of processing resources that might otherwise be available for encoding the speech content in memory.

Today and future NAND flash memory will heavily rely on system-level fault-tolerance techniques such as error correction code (ECC) to ensure the overall system storage integrity. Since ECC demands the storage of coding redundancy and hence degrades effective cell storage efficiency, it is highly desirable to use more powerful coding solutions that can maintain the system storage reliability at less coding redundancy. This has motivated a growing interest in the industry to search for alternatives to BCH code being used in today. Regardless to specific ECCs, it is of great practical importance to know the theoretical limit on the achievable cell storage efficiency, which motivates this work. We first develop an approximate NAND flash memory channel model that explicitly incorporates program/erase (P/E) cycling effects and cell-to-cell interference, based on which we then develop strategies for estimating the information-theoretical bounds on cell storage efficiency. We show that it can readily reveal the tradeoffs among cell storage efficiency, P/E cycling endurance, and retention limit, which can provide important insights for system designers. Finally, motivated by the dynamics of P/E cycling effect revealed by the information-theoretical study, we propose two memory system design techniques that can improve the average NAND flash memory programming speed and increase the total amount of user data that can be stored in NAND flash cell over its entire lifetime. [ABSTRACT FROM AUTHOR]

The computer industry may be accustomed to rapid change, but in the mass storage end of the business recently, the rate of progress has accelerated to an unprecedented clip. Historically. […]

Chips that implement video compression standards such as MPEG, JPEG, and P*64 could make everything from video phones to video teleconferencing a reality. But are these 'designed-by-committee' solutions the best […]

Rapidly advancing technology has always been a fact of life for computer designers, especially those working on the system core. In comparison, mass storage issues once looked simple. Sure, there […]

It started in the mainframe world over 20 years ago. In the late 1960s, IBM was building central processors that could cycle faster than big core memory planes. The architects […]