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Directed self-assembly (DSA) of block copolymers (BCP) has attracted considerable interest from the semiconductor industry because it can achieve semiconductor-relevant structures with a relatively simple process and low cost. However, the self-assembling structures can become kinetically trapped into defective states, which greatly impedes the implementation of DSA in high-volume manufacturing. Understanding the kinetics of defect annihilation is crucial to optimizing the process and eventually eliminating defects in DSA. Such kinetic experiments, however, are not commonly available in academic laboratories. To address this challenge, we perform a kinetic study of chemoepitaxy DSA in a 300 mm wafer fab, where the complete defectivity information at various annealing conditions can be readily captured. Through extensive statistical analysis, we reveal the statistical model of defect annihilation in DSA for the first time. The annihilation kinetics can be well described by a power law model, indicating that all dislocations can be removed by sufficiently long annealing time. We further develop image analysis algorithms to analyze the distribution of dislocation size and configurations and discover that the distribution stays relatively constant over time. The defect distribution is determined by the role of the guiding stripe, which is found to stabilize the defects. Although this study is based on polystyrene-b-poly(methyl methacrylate) (PS-b-PMMA), we anticipate that these findings can be readily applied to other BCP platforms as well.

Ultra-thin wafer fabrication has become a hot spot in recent years with the growing demand for small size and high performance electronic devices. However, far less research focused on the damage behavior in ultra-thin wafer. In this work, 300 mm diameter silicon wafer was thinned to 6 µm thick by grinding plus ultra-precision dry polishing. The damage behavior before and after the dry polishing was discussed. Mechanical and surface analysis showed that the dry polishing process can help improve the strength and surface uniformity of ultra-thin wafer by removing high pressure phase and micro cracks. Series of nano beam diffraction patterns revealed the stress induced by the thinning process only existed in surface. High resolution transmission electron microscopy images analyzed by geometric phase approach indicated that surface dislocations can move across the wafer and reached bottom device layers during the dry polishing, increasing the risk of electrical deterioration. The findings are of great significance to the study on process optimization of ultra-thin wafer and provide insights into the reliability of advanced electronic packaging.

The fan-out interposer (FOI) technology with fine pitch is demonstrated and presented for heterogeneous integration as a cost-effective and enabling technology. The co-design modeling methodology is established for the FOI technology, including wafer process-induced warpage, package assembly warpage, and board-level solder joint reliability to optimize the structure design, wafer process, assembly process, and material selection. Through the wafer warpage modeling, desirable glass carrier, photodielectric, and molding compound materials and interposer structure are suggested to reduce the wafer warpage. Effect of stiffener on assembly induced package warpage is simulated and studied. Board-level solder joint reliability is investigated and optimized based on the simulation results. The optimized materials and the structure design are determined based on the co-design modeling and simulation results to achieve the successful FOI wafer fabrication, assembly process, and board-level reliability for extreme large package with FOI.

The fabrication of ultrathin silicon wafers at low cost is crucial for advancing silicon electronics toward stretchability and flexibility. However, conventional fabrication techniques are inefficient because they sacrifice a large amount of substrate material. Thus, advanced silicon electronics that have been realized in laboratories cannot move forward to commercialization. Here, a fully bottom-up technique for producing a self-releasing ultrathin silicon wafer without sacrificing any of the substrate is presented. The key to this approach is a self-organized nanogap on the substrate fabricated by plasma-assisted epitaxial growth (plasma-epi) and subsequent hydrogen annealing. The wafer thickness can be independently controlled during the bulk growth after the formation of plasma-epi seed layer. In addition, semiconductor devices are realized using the ultrathin silicon wafer. Given the high scalability of plasma-epi and its compatibility with conventional semiconductor process, the proposed bottom-up wafer fabrication process will open a new route to developing advanced silicon electronics.

The semiconductor industry has entered a new era where monolithic integration cannot achieve the economic gains of silicon scaling. The role of chiplets is crucial in this new era by enabling cost reduction through the heterogenous integration of various functions and wafer fab technology nodes. Deca's planar M-Series™ surface is ideal for building highly integrated fan-out SoC (System on Chip) structures. Scaling to $2\mu \mathrm{m}$ lines & spaces and multiple redistribution layers (RDL) provides powerful new possibilities for IC designers. Chiplets can now be fabricated using the optimum wafer fab technology node providing the best performance with the most desirable commercial terms. In combination with Adaptive Patterning™, design rules for M-Series provide large via contacts on fine pitch chip interconnects. The scaling of M-Series for chiplets will be presented in this paper. The 2nd generation of M-Series starts with $2\mu \mathrm{m}$ lines & spaces using laser direct imaging (LDI) with up to four layers of Cu RDL delivering die to die interconnect of >200 wires/mm/layer. This breakthrough in high-density routing is achieved on a simple molded chips-first, chips-up structure without the need for complicated bridge chips in substrates. We will also present a breakthrough in device interface density with $20\mu \mathrm{m}$ pitch full array bond pads made possible with Adaptive Patterning (AP). This paper details the M-Series multi-chiplet fan-out structure with four Cu routing layers, all layers include $2\mu \mathrm{m}$ lines & spaces fabricated using LDI and Adaptive Patterning. The M-Series fan-out structure readily supports through-mold Cu posts if a 3D package on package (3D PoP) structure is required.

OCD (Optical Critical Dimension) is a sufficiently accurate and reliable metrology used in semiconductor industry. Understanding how to setup a proper library will not only help to give the measurements that is needed, it will also prevent unnecessary downtime to the wafer fab factory. In this paper, a multiple layer stack, Poly-ONO-Poly, was seen performing according to the usual baseline until there was a downward shift seen on an OCD parameter SWA (Side Wall Angle). We took some readings off the suspected processes, ETCH trim time and tool’s dependency and LITHO’s resist thickness correlation to try to understand more on their effects on SWA. However, there is little correlation seen from them to the effects on SWA. Simulations were then done to show the spectra’s relationship to the changes in the parameters: SWA, CD, HEIGHT. SWA was seen to have the least sensitivity to raw spectra versus CD and HEIGHT. This led to the suspicion that there was some changes in the spectra that caused the change in SWA, and thus leading us off the ETCH and LITHO into diffusion that could have changed the stack during ONO formation. It was thus found that ONO thickness has shifted. Once the thickness was tuned back to its original intent, SWA followed suit to recover to its measured units. This shows us that there’s a need to fully understand the library/spectra involved when using OCD.

Silicone wafer gripping and transportation have been widely utilized in wafer fabrication process, such as chemical mechanical polishing, grinding, epitaxial growth, etc. This paper develops a novel annular-shaped gripper based on Bernoulli effects with the aim of contactless gripping of large size and thin silicon wafer. The structural design and working principle of this annular-shaped Bernoulli gripper are presented. A computational fluid dynamic (CFD) model is established to study the adsorption performance of the gripper when gripping an 8-inch silicon wafer. Numerical simulation results showed that the gripper can generate an annular-shaped pressure distribution to adsorb the silicon wafer which can reduce the wafer's deformation. Then, the Bernoulli gripper was fabricated, and the 8-inch silicon wafer's gripping experiments demonstrated that the gripper has generally low suction curve gradient. Thus, the developed annular-shaped Bernoulli gripper could be utilized for contactless gripping and transportation of large-size and thin silicon wafers in potential industrial applications.

High-volume low-cost production of vertical cavity surface emitting lasers (VCSELs) will allow their exploitation in new commodity markets. We report the successful scaling up from research level fabrication to produce oxide confined VCSELs across a whole 150mm wafer. On-wafer light-current-voltage (L-I-V) and spectral measurements are analyzed to determine the cross-wafer variations in threshold current, threshold current densities and emission wavelength, which is compared with reflectivity measurements taken immediately after growth. We examine the dependence of VCSEL performance on fabrication parameters over a range of device dimensions to assess whether variation arises from non-uniformity of the epitaxial material or wafer processing.

Wafer fab mask inspection is facing new challenges in the era of Extreme Ultraviolet Lithography (EUVL). Mask qualification methods in use for ArF lithography are reticle verification based on wafer prints or defect inspection on Deep Ultraviolet (DUV) mask inspection tools. The latter is the industry preference in most cases. To implement this established methodology for EUV masks with pellicle, the pellicle must have transmission that enables inspection for defect detection. In this work we test the viability of a DUV mask inspection platform to image and inspect an EUV mask with a Carbon Nanotube (CNT) based pellicle [1]. Pellicles are used to keep particles off the patterned side of the photomask. For DUV and longer exposure wavelengths, polymers with transmission above 99% are routine. For EUV wavelengths, identifying a transparent, mechanically robust film that is compatible with EUV exposure environments has been challenging. Commercially-available EUV pellicles for lithography are p-Si based[2]. This pellicle type achieves the critical protection of the mask but induces a significant productivity loss due to EUV light absorption. The critical need for a highly-transmissive pellicle will increase with advanced nodes that put more pressure on uniformity specifications and throughput. In this arena, CNT based pellicles exceed the required transmission for High-Volume Manufacturing (HVM) and show promise towards production adoption [3]. DUV light absorption is relevant for mask inspection. DUV light is absorbed by the p-Si pellicle, while the CNT has high transmission in this wavelength region as well, making mask inspection of EUV masks with pellicles possible on existing DUV inspection tools, such as Applied Materials Aera5TM. In order to understand the impact of CNT pellicle on DUV inspection, a controlled study was performed by Applied Materials in cooperation with imec. The study consisted of various system measurements and extensive application qualification. Aera5TM inspection results on a Programmed Defect Mask (PDM) with a full field CNT pellicle will be presented. The results with pellicle are comparable to the reference no-pellicle inspection and meet the same detection sensitivity. Detection optimization Best-Known Methods (BKM) developed on EUV masks without pellicles proved to be effective. These include, but are not limited to, aperture shaping, defocus and polarization. Moreover, the imaging and main system components performance were examined, and no impact was observed.

In the proposed study we demonstrate the elimination of helium as a wafer cooling gas in plasma enhanced chemical vapor deposition (PECVD) wafer fabrication equipment (WFE). Key technical challenges were addressed by using proprietary helium elimination hardware and software. The helium elimination upgrade proved to be compatible over a wide array of applications after testing multiple PECVD processes without any observed negative impact to process performance or throughput. By incorporating this technology in Lam’s VECTOR® system, end users can expect to save approximately 5L of He per wafer processed, resulting in substantial savings in the overall cost of manufacturing integrated circuits (ICs).

We have developed novel compact suspended stripline filters and low-loss passives based on MMIC wafer fabrication techniques and heterogeneous integration through gold-gold compression bonds. The key features are high precision, on-wafer testable for known-good-die, and high electromagnetic isolation. This approach is best suited to designs in the range of 0.5-100 GHz. As an example of applying this novel capability, a 0–11 GHz & 11–22 GHz contiguous diplexer filter was designed and fabricated to produce a SiC center-conductor die which is bonded and suspended in gold-plated silicon ground cavities using heterogeneous integration. EM modeling accurately predicts filter performance and multiple fabricated copies of the filter have near-identical S-parameters characteristics.

In this work, the authors evaluated the access resistance of InP high electron mobility transistors (HEMTs) and their degradation during wafer processing. The transfer resistance, which was rarely separated from other components of the total access resistance of InP HEMTs in the literature, was found to be the dominant component of the access resistance. It was also found that the transfer resistance degraded during wafer processing. The selection of the ohmic metal stack and its impact on both the metal-cap contact resistance and the transfer resistance was also investigated. The observations in their experiments and relevant discussions in the report are expected to be useful in the identification of improvement opportunities in both material growth and wafer fabrication of InP HEMTs.

Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. In fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. For these RDL barrier/seed layers, PVD cluster tools, wafer transport architectures that have been widely used since the mid-1980s, are the current Process of Record (POR) in advanced packaging; however, these tools typically operate in a regime where wafer transport is robot-limited to approximately 50 wafers per hour, which limits overall throughput and greatly influences Cost of Ownership (COO) for the sputter deposition step(s), because the central handling robot occupied with a transfer from the Ti PVD module to the Cu PVD module, for example, has no opportunity to be doing anything other than that specific transfer. Other wafer transport architectures are more efficient from a wafer handling perspective. In linear transport carrier-based PVD tools, wafers or panels passing through the system benefit from a mechanical transfer time budget that is considerably less than for a cluster tool. Transport time overhead per wafer on linear transport systems is quite low, and scheduler software optimization becomes less onerous too, as a result of the simpler wafer transport architecture. We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition process, and present details here of how the time spent moving wafers to various processing chambers affects overall system productivity. In the case of the cluster tool architecture, with its central wafer handling robot, wafer throughputs are approximately 50 wafers per hour, while on the linear transport system wafer throughputs as high as 240 wafers per hour are possible. The significant difference in system throughputs greatly affects the relative Cost of Ownership (COO) per wafer processed, with the linear transport system returning COO results that are less than half those of the typical cluster PVD tool.

A semiconductor wafer undergoes various processing steps before it is transformed from a plain silicon wafer to one populated with thousands of integrated circuits. Each of these processing steps is susceptible to specific types of defects. Some defects may not be captured by in-line inspection tools or may not be sampled during defect review-scanning electron microscope and are carried over multiple processing steps. Such defects can be discovered at the end of the fabrication procedure, which requires process engineers to trace back the manufacturing processes that caused these defects. Despite the success of most current methods that detect defects during wafer fabrication, most of these methods are inable to accurately associate the source of an individual defect type to a specific semiconductor processing step. We believe that this limitation can be overcome by considering the carry-over of defect signatures rather than individual defects. We propose in this paper a system called step-defect contribution analyzer (SDCA) that detects defect signatures on semiconductor wafers and overcomes the limitations outlined above. SDCA allows process engineers to trace back and associate the source of a final defectivity discovered at the end of the fabrication procedure to specific defect signatures carried over multiple process zones. We experimentally evaluated the quality of SDCA by measuring its prediction accuracy. Results revealed marked prediction accuracy.

We demonstrated mainly some of the different parameters effects -as a function of temperature-as window layers, thickness, and doping of the various layers (emitter, base and BSF) on the performances of InGaP/GaAs solar cell. First, we have varied the molar fraction of different layers; their thickness and the doping of both emitters and bases. We have registered the result of each variation until obtaining optimal parameters. In a second stage, we have simulated the InGaP/GaAs cell without window layers which results in η = 12.47% and η = 22.14% for eliminating top and bottom windows respectively. Then, the elimination of layer BSFs(back surface field) on the back face of the considered cell causes a remarkable decrease in open circuit voltage Voc and output η which reached 1.57 V and 11.95% respectively. In a last stage, we optimized and simulated the performances of the InGaP/GaAs dual-junction solar cell for its optimal parameters while varying its operation temperature from 300 K to 375 K with an increment of 25 °C using a virtual wafer fabrication TCAD Silvaco. The optimization at 300 K led to the following results Icc = 15.19 mA/cm−2, Voc = 2.53 V, FF = 91.32% and η = 25.43% which are close with those found in literature for In(1−x)Ga(x)P(x is molar fraction: x = 0.5). Therefore, we could determine the critical parameters of the cell and optimize its main parameters to obtain the highest performance for a dual junction solar cell. This work will pave the way with new prospects in the field of the photovoltaic. The structure simulation will simplify the manufacturing processes of solar cells; will thus reduce the costs while producing high outputs of photovoltaic conversion.

Solder bonding and Cu-Cu bonding are studied and compared to see which method is the best packaging solution for 3D IC packaging. By using real memory wafers, a typical 3D IC structure of 4-layer chip stacking are built up by the two bonding methods. The comparison covers design, wafer fabrication, assembly and reliability.

High temperature baking treatment is a method to remove chemical residue on mask before shipping to wafer fab. When developing advanced mask technology, we need to make sure the bake treatment have no side-effect to mask quality. In this investigation, some test has been devised to study the relation between baking process and mask registration, CD movement, repaired point, ion residue and cleaning performance. We also studied how to setup a stable and efficient bake process to make the mask making flow reasonable. The high temperature bake processes was tuned by different temperature, treatment loops setting and was put at different process position to verify the performance. In this paper, OMOG and EAPSM masks were chosen to test by different process condition.

Thermal oxidation is a process done to grow a layer of oxide on the surface of a silicon wafer at elevated temperatures to form silicon dioxide. Usually, it en- counters instability in oxide growth and results in variation in the oxide thickness formed. This leads to downtime of furnace and wafer scrap. This study focuses on the factors leading to this phenomenon and finding the optimum settings of these factors. The factors that cause instability to oxide thickness were narrowed down to location of wafer in furnace, oxidation time, gas flow rate and temperature. Characterization and optimization were done using Design of Experiments. Full factorial design was implemented using 4 factors and 2 levels, resulting in 16 runs. Data analysis was done using Multiple Regression Analysis in JMP software. Actual versus predicted plot is examined to determine whether the model fit is significant. Adjusted R2 value was obtained at 99.8% or 0.998 indicating that there is very minimal variation of the data not explained by the model and thus confirming that the model is good. From the effect test, the factors were narrowed down from 4 factors to 3 factors. Location factor was found to have no impact. Significant factors that have impact are gas flow rate, oxidation time and temperature. Analyzing the leverage plots and least square mean plots, temperature was found to have the highest impact on oxide thickness. The model was further analyzed using prediction profiler in JMP to find the optimum settings for thermal oxidation process to meet the target oxide thickness of 8000A. Optimum setting for temperature was found to be at 958 C, gas flow rate at low flow rate (H2:6.5 slm and O2:4.5 slm), oxidation time at 280 min and location of wafers at both zone 1 and zone 2.

This paper presents the influence of top-gate dielectric material for graphene field-effect transistor (GFET) using TCAD simulation. Apart from silicon-based dielectric that is typically used for top-gate structure, other high-dielectric constant (high-k) dielectric materials namely aluminum oxide and hafnium oxide are also involved in the analysis deliberately to improve the electrical properties of the GFET. The unique GFET current-voltage characteristics against several top-gate dielectric thicknesses are also investigated to guide the wafer fabrication engineers during the process optimization stage. The improvement to critical electrical parameters of GFET in terms of higher saturation drain current and greater on/off current ratio shows that the use of high-k dielectric material with very thin oxide layer is absolutely necessary.

The polysilicon is a material widely used in an many electronic components. When circuits are placed underneath the bond pads, it is expected that their electrical properties are not impacted by any kind of thermo-mechanical stress. This paper presents detailed investigation of such various Back End Of Line (BEOL) stress impacts on a polysilicon material. A meander shaped polysilicon resistor was used as a test vehicle. In this paper, various factors (number of probe insertions, probing temperature and wire bond material) were investigated to determine the impact on the electrical properties of the polysilicon circuit. The change in resistance of the polysilicon resistors after probing and wire bonding were measured. The change in resistance was observed to be negligible after probing. After wire bonding there was a significant change but seen only ~ 3%. However, it must be noted that this percentage change in resistance is still well within the reliability specification limit, which have been followed by industry.

Coherency analysis is adopted in this paper to examine the linear dependence between measurements of three processing parameters during wafer fabrication process. They are power, pressure and voltage measurements and three channels from optical emission spectrum data. The measurement data were divided into consecutive short data segments to provide time-stamped coherence signatures. Our results observe significant linear dependence appeared in multiple harmonic frequencies. The linear dependence appears in the beginning of the processing step and continues toward the end. The verified linear relationship between process parameters sheds the light for redundancy reduction and more compact data representation.

Defect density in wafer fabrication can be a significant source of yield loss and reliability risk especially as device feature size shrinks. Thus to identify the root cause of the defect and eliminate them effectively is very crucial. The mechanism of a defect density called polysilicon residues and the key processes that affect this defect are studied in the paper. This defect of interest was generated due to watermark formation on the hydrophobic polysilicon surface, the silicate precipitate from the watermark acts as an unwanted masking layer causing block etch to the subsequent polysilicon etch resulted in poly silicon residues. The watermark was found after the de-ionized water rinse step. Avoiding the wafer to be exposed to ambient air after the water rinse has been adopted as key solution to prevent the watermark formation and hence eliminating the polysilicon residues.

This work presents a fully functional miniaturized MEMS microphone demonstrator assembled within a modified Fan Out Wafer Level Package (FOWLP) process chain. Core of the development is the adaption of the FOWLP-process to MEMS-microphones, which have not yet been fully processed in the wafer fab. Instead, these microphone chips contain non-released membranes making them sufficiently robust to withstand backend processes, such as laminating and molding. The membrane release itself is performed on the reconstituted mold-wafer and postponed to a later process step. Mechanical stress effects induced by the package onto the MEMS are limited to a minimum by the implementation of stress decoupling suspension structures on the MEMS die.

Standard wafers with programmed defects (PDs) were fabricated to evaluate charge control techniques, resolution, and defect detection capabilities of pattern inspection tools for 7-nm and smaller nodes. To evaluate charge control techniques, the PDs were formed in line and space (LS) patterns. PDs were also formed below contact holes as programmed etching residues. These PDs were detected by a voltage contrast inspection technique. Image distortion by charging was also evaluated with the use of a wafer in a multibeam secondary electron microscope (SEM) and projection type inspection systems. Patterns with PDs were also formed on different subsurface structures. The effects of subsurface structures on the defect detection capability were evaluated based on this wafer. Another type of wafer having small defects approximately 5 nm in size on 16- to 12-nm half pitch (hp) LS patterns on a 12-inch Si-wafer, was fabricated by electron beam lithography. This wafer allowed evaluation of the defect detection capability of PDs having different shapes and sizes, such as protrusion, intrusion, bridge and open defects, on dense patterns for 7-nm and smaller nodes. Moreover, extremely small protrusion defects, with a size of 1 nm, and small bridge defects (as narrow as 1 nm) were also fabricated into LS patterns with ultra-low line-edge-roughness on a Si (110) substrate. This patterned substrate was mounted into a 12-inch Si wafer, and we evaluated the performance of tools for 12-inch wafer fabrication. We proposed a method to verify the true LER/LWR by CD-SEM measurements.

Boron and phosphorus contaminants are difficult to detect in cleanrooms for semiconductor manufacturing due to their typically low concentration levels. In this paper, a new technique for detecting such contaminants that significantly reduces sampling time, from 24 h to less than 2 h, and avoids wafer congenital contamination interference, is proposed. An oversaturated nucleation approach extracts boron and phosphorus contaminants to show regional contaminant concentration differences rapidly. This method is simple, express, robust, and reliable. Moreover, it has been tested on site in wafer fabrication plants. The generic sampling framework can be refined and applied to metallic, dopant and other low-concentration contaminants in cleanrooms.

In order to reduce the material cost for silicon solar cells, several research groups are investigating methods to minimize the silicon consumption for making monocrystalline silicon wafers. One promising approach is deposition of an epitaxial layer on porous silicon, followed by detachment of the layer. This contribution discusses improvements in the epitaxial wafer fabrication by optimization of the porosification process. The introduction of a layered porous silicon structure allows to independently improve both epitaxial layer quality and detachment yield. In this way, we have managed to obtain 100µm thick silicon wafers with effective lifetimes up to 1.3ms, and 40µm thick wafers with effective lifetimes up to 700µs. We will also review the current status of the process development for solar cells made on thin wafers. Two approaches are presented. In the first approach, heterojunction solar cells are fabricated on freestanding epitaxial wafers of 40µm thickness. In the second approach, high efficiency (21%) heterojunction back-contacted cells are fabricated on wafers that are bonded to a glass superstrate. Challenges for device processing and limitations in cell performance are discussed.

High Via resistance for borderless Via design was detected at PCM E-test step during wafer fabrication. The high via resistance wafers were sent for TEM and EDX analysis to determine the failure root cause. From the TEM images, a layer of non-conductive material is seen at the Via hole bottom. EDX analysis and probe spectrum analysis confirmed the foreign material is Al-F-O compound. A Design of Experiment (DOE) was carried out to determine the dominant factor contributing to the formation of the Al-F-O material after post Via etch clean.

The developments in electronics technology push the invention of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) towards smaller physical dimension with improvements in both quality and performance. In this paper, design, fabrication and simulation of electrical characteristics of 14nm La 2 O 3 /WSi 2 NMOS is presented. The fabrication and simulation process of device were performed by using Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools, which consists of ATHENA and ATLAS. The designed device was optimized using Taguchi Method that involves orthogonal arrays and analysis of variance (ANOVA). The original results before optimization process for V TH is 0.212648V (7.5% lower than the targeted value) and I OFF is 3.73851×10−9 A/μm while the optimized results for V TH is 0.233321 V (1.44 % higher than the targeted value) and I OFF is 4.732375×10−11 A/Δm which fulfilled the targets based on International Technology Roadmap for Semiconductors (ITRS) 2013. The Taguchi optimization method yields a significantly lower I OFF with an improved I ON /I OFF ratio by a factor of 25.

Ongoing miniaturization in process node technology used in fabricating integrated circuits (ICs) has enhanced chip performance but at the same time this has induced subtle defects. As a result, Failure Analysis (FA) has become increasingly important for root cause analysis to enable wafer fab process improvement. This paper presents a novel FA approach on real case Scan Chain functional failure induced in fabrication process by incorporating Focused Ion Beam (FIB) circuit edit, Infrared Emission Microscopy (IREM), extensive layout study, Nanoprobing, Electron Beam Absorbed Current (EBAC), Transmission Electron Microscopy (TEM) and Energy Dispersive X-ray (EDX) for defect localization.

This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.

Short-flow electrical test structures are extremely useful for determining the effect of certain process conditions on process defectivity. Thus, the test structure can be used to test the result of changes made to a process condition specifically to reduce the number of defects. Because they can be processed in a relatively short time, short-flow structures can also be used as realtime process-monitoring and process-control tools. The gate oxide dielectric is the heart of a metal oxide semiconductor (MOS) or complementary MOS (CMOS) integrated circuit. Gate oxide integrity tests can vary widely in terms of the specific capacitor structures and the criteria for evaluation. Examples of various types of capacitor structures are: areas/perimeters; blocks or stripes (edge effects); with or without field oxide; and with or without sidewall oxide. There are many contamination and defect sources within an entire wafer fabrication process.

As portable electronic products toward thinner form-factor with higher integrated functionality and performance, adopting advanced Cu with extreme Low-k inter-metal-dielectric material (ELK IMD) wafer fabrication technology, such as 28nm technology, and WLCSP packaging with large die size become the trend in fulfilling high-end product demands. To investigate 28nm wafer WLCSP board level reliability performance is essential and critical for successful product launch and preventing field return risk. 28nm test vehicles were used with combinations in different die sizes, 3.5x3.5 mm2 and 6x6 mm2, and different solder ball compositions, SAC405, LF35, LF35+2%Bi and SACQ, to understand solder ball alloy effect and potential impact on board level reliability. TCB 200cycle test showed, for 6x6 mm2 test vehicle, SACQ solder ball split showed no ball crack open risk and the other solder ball splits showed ~ 29% - 62% ball crack open defect risk. On the contrary. for 3.5x3.5 mm2 test vehicle, all solder ball splits showed no solder ball crack open risk except for SACQ solder ball split which encountered 33% solder joint crack open risk. A quick stress test methodology using 75 cycles of -650C~1500C liquid-to-liquid thermal shock (LLTS), showing ~acceleration factor of 1.9 compared with TCB stress, was validated and used for shortening experiment cycle time. A 5x5 mm2 test vehicle was used for different underfill fillet height evaluation to assess board level reliability impact, mainly no underfill, negative, zero and 100% filet height conditions. LLTS 75cycles result showed zero and negative underfill filet height splits with die edge ELK delamination defects. A package stress modeling was performed and showed the highest WLCSP ELK stress with zero underfill filet height condition, followed by negative filet height and 100% filet height conditions. The results well matched with experimental results.

A wire pull test Finite Element Analysis (FEA) simulation enabled better insight into the role of both wafer fabrication Back End of Line (BEOL) as well as package level wire material in causing bond pad lift/peeling failure. In this work, it was discovered that wire material change had a greater impact to the BEOL stress compared to the BEOL design itself. Alternate BEOL designs need to be continuously evaluated prior to introduction to the bond pad design. FEA simulation can alleviate the prototyping phase by narrowing down the number of samples required for testing.

In the last decades the semiconductor technology has been driven by Moore’s law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP’s 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA’s into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP’s 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP’s standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

This study evaluated the potential for cutaneous exposures to engineered nanometal oxides from workplace surfaces in a semiconductor research and development facility. Exposure assessment methodology captured engineered nanomaterials (ENMs) from work surfaces accessible for worker contact via the skin that were associated with chemical mechanical planarization (CMP), a polishing process utilized in semiconductor fabrication. A microvacuum approach was used to collect surface samples for morphological analysis via transmission electron microscopy (TEM) and scanning electron microscopy (SEM), both with energy-dispersive X-ray spectroscopy (EDS) for compositional analysis. Eleven surface samples were collected along the CMP lifecycle: 1 from the cleanroom (“fab”) where wafer fabrication takes place, 4 from the subfab where bulk chemical delivery systems are located, and 6 from the wastewater treatment (WWT) area where CMP wastewater is treated and discharged. Engineered nanomaterials of interest (Si, Al, Ce) were found from all areas of collection, existing as particles or agglomerates (>100 nm). Results support the findings of prior research and indicate that nanomaterials utilized or generated by CMP are found on work surfaces and may be accessible for cutaneous exposure by workers in semiconductor facilities. In order to minimize and/or prevent cutaneous exposures for workers who use or handle ENMs in this industry, prudent preventive work practices should be followed, including use of personal protective equipment, hazard communication, and engineering and administrative controls.

Quantitative characterization of local strain in silicon wafers is critical in view of issues such as wafer handling during manufacturing and strain engineering. In this work, full-field X-ray microdiffraction imaging using synchrotron radiation is employed to investigate the long-range distribution of strain fields in silicon wafers induced by indents under different conditions in order to simulate wafer fabrication damage. The technique provides a detailed quantitative mapping of strain and defect characterization at the micrometer spatial resolution and holds some advantages over conventional methods.

The cleaning process of the silicon wafer becomes one of the most important procedures in semiconductor fabrication. It is acknowledged to remove the contamination on the wafer surface as well as to promote an acceptable surface roughness, prior to performing various deposition methods. The wafer cleaning process which based on hot alkaline and acidic solutions is known as the RCA cleaning. The RCA is still the most important wafer cleaning method used in wafer fabrication industry. In this paper, the effects of various cleaning procedure to the silicon wafer surface roughness are measured using AFM. Subsequently, an optimum cleaning recipe is discussed and proposed.

The high capital expenditure (capex) necessary to manufacture crystalline silicon PV modules negatively affects the levelized cost of electricity (¢/kWh) and critically impacts the rate at which the PV industry can scale up. Wafer, cell, and module fabrication with thin free-standing silicon wafers is one key to reduce capex. Thin wafers reduce capex associated with silicon refining and wafer fabrication, which together sum to 58% of the total capex of silicon module manufacturing. In addition, thin wafers directly and significantly reduce variable costs. However, introducing 50 μm thin free-standing wafers into today's manufacturing lines result in cracking, creating a yield-based disincentive. Due to the brittle nature of silicon, wafer breakage is the major concern due to the high stress that is induced during processes in manufacturing lines. In this paper, we describe an improved method for edge micro-crack detection that can help enable low-capex, thin free-standing Si wafers. We present a method of detecting and measuring cracks along wafer edges by using a dark-field IR scattering imaging technique which enables detection of edge cracks at the micron scale. Keywords: Capex; polysilicon; thin free-standing wafer; edge crack detection; IR scattering; dark-field imaging, United States. Department of Energy (Grant DE-EE0007535)

In this paper, we studied the Al bondpad qualification methodologies and application in backend process optimization and improvement so as to provide good quality bondpads and wafers in wafer fabrication. The three Al bondpad qualification methodologies including OSAT, SLAT and Wafer Die Sawing Test were introduced and discussed.

Thin film deposition process invariably introduces compressive or tensile stress in the films. The stress in a film causes the wafer to warp whose curvature is estimated in a wafer fab using optical reflectance technique. Alternatively, the wafer curvature can also be measured using the high resolution XRD (HRXRD) Si(004) rocking curves. In this paper, the HRXRD technique was employed to evaluate the stress in PECVD and HDP SiN films deposited on blanket Si wafers (prime-grade material) which were subjected to different Xe ion-implant energy conditions. It will be shown that stress-matching in PECVD and HDP SiN can be achieved by tuning Xe implant energy. From the change in the width of Si(004) peak, a qualitative assessment regarding the quality of single crystal Si lattice will be presented which is not possible to measure with optical reflectance methods.

Failure Analysis (FA) consists of fault verification, isolation, defect tracing, characterization and physical (elemental) analysis. It helps wafer fab to understand the root causes of low yield cases, drive the yield improvement activities. Due to the complexity of modern Integrated Circuits (ICs), defects causing the failure need more effort, a variety of FA tools to be identified. In this case, a case of wafer center patch failure was studied. First of all, failure mode was identified through datalog study, which identified the majority of the center dies failed in leakage bin. The subsequent electrical fault isolation was performed by IV measurement and Thermal Induced Voltage Alteration (TIVA). The defect signal was found at unique structure for different failure dies, which was known to be poly resistor structure after layout study. After that, top-down physical analysis was then carried out using several FA techniques such as delayering, Scanning Electron Microscope (SEM) inspection, Passive Voltage Contrast (PVC), Atomic Force Probing (AFP), cross-sectional approach was also carried out using Focus Ion Beam (FIB) and Transmission Electron Microscope (TEM). In the end the defect was found to be unwanted salicadation at the side wall of the poly resistor, due to process-related issue. With the help of FA findings, Fab was beneficial in identifying the related process causing this faiure.

We introduce a system called IDS for diagnosing semiconductor fabrication process. IDS can identify the carry-over defect that contributed to a defective cluster captured by an in-line inspection tool during a specific fabrication processing step. Let R x be a defective cluster captured by an in-line inspection tool during the fabrication processing step ps i . First, IDS would identify the defect type of R x by comparing the image of R x with the images in reference wafer maps of previous defect clusters captured at psi. Let dj be the identified defect type. IDS would use rules of inferences for identifying the root cause of dj. It will utilize d j as a trigger for the appropriate defect specification rules using the standard rules of inferences. By applying the defect specification rules recursively using the inference rules, IDS can identify the root cause of d j . We experimentally evaluated the quality of IDS. Results revealed marked prediction accuracy.

Silicon Photonics is a promising new technology for realizing efficient, high performance interconnects. There is a growing need for educating future engineers on how to design, fabricate, test and package Silicon photonic circuits. Here we demonstrate a Silicon photonic process suitable for an educational institution with i-line lithography capabilities. We have developed a suitable process for realizing passive photonic devices (i.e. waveguides, interferometric structures and fiber-chip grating couplers). The process is realized in a CMOS compatible environment which has been in use since 1986 to teach microelectronic engineering. And is now also being used to support the AIM Photonics Academy education mission. Specifically, an array of TM-polarized grating couplers with a ring resonator was fabricated with a lithographic resolution of 0.325 µm on an SOI wafer. The setup time and run time required was 3 days in comparison to the long wait time in the industry. Optimization of the resolution using ARC i-CON-7, diluted OiR 620 and the etch selectivity of the Silicon to the 1∶1 OiR 620:PGMEA was key to the student run fabrication process and is supported by the Optical microscope and SEM results.

Plasma etching is commonly employed in the chemical etching process of wafer fabrication because of its low cost and good control of etching profile and uniformity. In the plamas etching process, particle per wafer pass (PWP) test will be carried out periodically to reduce chamber contamination. When the number of particles exceeds a predefined threshold, the chamber must be wet-cleaned. Unfortunately, in actual manufacturing, the gaseous recipes used during etching vary with the etched materials, producing unexpected by-products, and render the particle count from PWP highly stochastic. Consequently, the high particle counts could exceed the threshold before the scheduled wet-clean maintenance, resulting in an unexpected high-yield loss. In this paper, we analyze the daily PWP results from an inductively coupled plasma etching (ICP) chamber. The behavior of the particle counts is modeled as a stochastic function of the accumulated gaseous flowing though the chamber. The particle count is found to follow a negative binomial (NB) distribution. The parameters of the NB distribution are determined from the industrial data, and with these parameters, we determine the optimal schedule for the wet-clean process with significant reduction in the failure occurrence.

Background: Standard patterned sample with programed defects (PDs) is effective to evaluate the tool performance of pattern inspection system, but the fabrication of such standard sample, having large area dense patterns with PDs suitable for the evaluation of sub-7-nm node, is difficult. Aim: The goal of this study is to fabricate a standard sample to evaluate the performance of inspection tool for below 7-nm nodes. Approach: We use electron beam lithography with an acceleration voltage of 130 keV to fabricate standard sample. Results: We form large area dense sub-16-nm half pitch (hp) line and space (LS) patterns with PDs on 300-mm-Si-wafers, and 10- to 7-nm hp LS patterns on a 100-mm-Si wafer. Approximately 5-nm PDs with shapes including protrusions, intrusions, bridges, and openings are formed without additional defects. Moreover, pattern-etched Si wafers with 16- to 12-nm hp LS are successfully fabricated. A 100-mm-wafer with patterns is mounted into a 300-mm-Si wafer. Conclusions: The acceleration voltage of 130 keV is sufficient for the fabrication of large area dense pattern with PDs suitable for the evaluation of sub-7-nm node. Moreover, the fabricated standard wafers are useful to evaluate the tool performance of the inspection system for 300-mm wafer fabrication.

During the wafer fabrication process, wafers warp into different kinds of shapes, such as spherical, cylindrical, or saddles. These wafers may exhibit a bistable state, that is, if we apply a certain amount of pressure, they snap into another state. Though these shapes are commonly observed in the real world, we have found that it is extremely difficult to obtain these shapes in finite-element tools, such as ANSYS, because some of these states are not numerically preferred solutions. In this paper, we discuss various methodologies we have used to obtain these shapes in ANSYS. The experiments have been carried out in our fabrication lab to measure the wafer warpage at various stages of wafer fabrication. We have found that when the simulated shape matches the experiment, the warpage or maximum out of plane displacement of the wafer obtained from our simulation matches with 1% with the experimental results as well. Furthermore, ANSYS simulations show that backgrinding increases the warpage by the same amount as observed in the experiments. This paper also discusses the limitations of Stoney's formula. The final goal of this paper is to predict how warpage is going to affect the stresses in the silicon (Si) trenches in a device and if any particular trench design is going to lower the amount of wafer warpage, hence the stresses in Si trenches. Section IV shows the simulation results of stresses in the Si trenches. Since it would be computationally infeasible to model a full wafer having all the details of the trench structures, a submodeling technique has been adopted to calculate the stresses in the Si trench wall of a warped wafer. These simulation results are compared with micro-Raman spectroscopy measurements of a warped wafer.