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Thyristors operated at switching point are highly sensitive to external physical signals such as light or temperature. However, due to the instability of sensitive switching point, conventional thyristors are commonly used as optical switches and hardly applied for low-light level detection. In this work, a silicon-based gate-controlled lateral thyristor (GC-LT), which takes advantage of high sensitivity at low-light, is studied by numerical simulation. A thyristor photodetector circuit and a novel super-off Reset operation method are also proposed to bias the GC-LT over the switching point quickly and allow the photodetector to be operated in a monotonic dynamic multi-sampling mode to achieve high sensitivity to low-light. Simulation results show that the Reset time can be shortened to $ < 10~\mu \text{s}$ without trigging the GC-LT. The trigger time of the photodetector is sensitive to the optical power density ranging from $1\times 10^{-9}$ to $2.5\times 10^{-6}$ W/cm2. Furthermore, the average optical gain is about 8.0-6.3, approximately one order of magnitude higher than that of the Si pinned photodiode.

Exposure to a magnetic field at room temperature was found able to promote the dislocation motion and distortion relaxation in silicon. The Kernel average misorientation maps of the silicon samples obtained by electron backscatter diffraction (EBSD) showed that a magnetic field ∼1 T can cause dislocation movement of hundreds of nanometers. And the EBSD image quality maps indicated that the magnetic field can cause the relaxation of the lattice distortion. The Δgmechanism of the magnetically stimulated changes was discussed.

This paper presents a new microplasma generator that can discharge helium gas to produce microplasma with ultra-low breakdown voltages at atmospheric pressure. The generator consists of 2 planar metal electrode arrays and a micro flow channel above the electrodes. The electrode arrays create high electric fields at the electrode gap by applying an AC voltage, which breakdown the working gas flowing through the micro channel. The new generator with low discharge voltages is inspired by the phenomenon discovered in experiments that the discharge voltage decreases when using flowing working gas. Experiments shows that the generator is able to generate stable atmospheric plasmas with a discharge voltage as low as 197 V and a low power consumption of 45 mW; both are the lowest results in literature reports.

This paper reports the design, fabrication, and test of a novel coaxial through-silicon-via (TSV) using low-κ SiO 2 insulator and fabricated on normal silicon substrate for high-frequency applications. The coaxial TSV consists of an annular Cu conductor deposited on the outer sidewall of a central Si post, an annular Cu shielding layer deposited on the inner sidewall of an annular trench that surrounds the Si post, and an annular low-κ SiO 2 insulator in-between the two Cu layers. The low-κ SiO 2 insulator, with the advantage of low cost and good high-frequency performance, is formed by vacuum-assisted spinfilling and thermal curing of liquid precursors. The Cu shielding layer prevents the propagation of electric fields into the lossy silicon substrate and blocks external interferences, and the low-κ SiO 2 insulator reduces the dielectric loss and the parasitics of the TSVs. The measured S 21 and S 11 of TSVs are, respectively, -0.48 dB and -14.91 dB at 10 GHz, and are -1.48 dB and -11.73 dB at 40 GHz, indicating that the coaxial TSVs achieve excellent propagation properties at high-frequency that are impossible for normal TSVs.

This paper reports the design, fabrication, and test of a 3-D integrated uncooled focal plane array (FPA) using monocrystalline silicon diodes as thermosensitive devices. The diode array is fabricated from the silicon device layer of a silicon-on-insulator wafer, and the readout integrated circuits (ROICs) are fabricated on a bulk wafer using the CMOS technology. The silicon diode array is vertically integrated with the ROIC using the 3-D integration technology. Electroless nickel (Ni) plating is developed for fabricating substantial Ni posts to mechanically support the diode pixels to suspension and electrically connect the diode pixels to the ROIC. It allows the integration of monocrystalline device arrays with CMOS circuits fabricated using separate technologies and wafers in vertically suspended configuration. It also improves the filling factors of the FPA chips, shortens the wires between the diodes and the ROIC, and facilitates the releasing process to suspend the diode array. A $160 \times 120$ small-scale FPA has been developed as a test vehicle for concept verification. The test results and successful thermal imaging demonstrate the feasibility of the 3-D integration technology and verify the application of 3-D integration in the development of integrated FPAs using monocrystalline thermosensitive devices.

Silicon nanowire (SiNW) field-effect transistors (FETs) have been developed as various bio/chemical sensors due to their high sensitivity as a result of the huge surface-to-volume ratios. This paper presents a CMOS compatible sidewall mask technology (SMT) for top-down fabrication of SiNWs and a highly sensitive pH sensor based on SiNW FETs. The essence of SMT is to use stand-alone vertical sidewalls of a conformal thin film, fabricated by anisotropically etching away the planar part of the thin film deposited on a thin mesa, as hard masks for SiNW etching. As the feature size of the sidewalls, depending on the film thickness rather than lithography, can be controlled readily to tens to hundreds of nanometers by tailoring the film thickness, SMT allows high output and low cost fabrication of SiNWs without need of advanced lithography facilities. Complete SMT processes have been developed for fabrication of SiNW FETs, and pH sensors using SiNW FETs have been realized. Measurement results show that the pH sensors have good static characteristics and transient performance, and the sensitivity reaches 54.5 mV/pH for a wide range of pH values from 1 to 12, approaching the theoretical Nernstian limit.

To lower the bonding temperature and save the time of the Cu-Cu bonding applied for 3D integration, Ag nanostructure was deposited on the Cu pads as intermediate by femtosecond pulsed laser deposition (PLD). The interface morphology after bonding including oxidation detection and microstructure evolution during high-temperature storage was investigated. The underlying bonding mechanisms were then analyzed and concluded. The element distribution of Ag nanostructures after PLD deposition is detected using the scanning transmission electron microscope equipped with energy dispersive X-ray spectroscopy mapping, and no oxygen is found inside the nanostructures. The electron energy loss spectroscopy shows that no oxidation happens across the Cu-Ag-Cu bonding interfaces during the bonding process by observing the same chemical state of Ag and Cu as the pure metal atom. The as-bonded Cu-Ag-Cu samples were stored at the temperature of 200 °C for 500 h and the microstructure at the bonding interface was observed. Based on the interface microstructure and crystal structure, the physical mechanisms of Cu-Cu bonding using Ag nanostructure as intermediate was explored and summarized in detail. The mechanical interlock between Ag nanostructures, large plastic deformation, surface melting and bulk diffusion are found to simultaneously contribute to the bonding.

This paper reports reactive ion etching (RIE) of poly (cyclohexene carbonate) (PCC), a thermal decomposable polymer that can be used as a sacrificial material for fabrication of embedded micro cavities and channels. The dependence of etching rate and anisotropy on RF power, chamber pressure, and O 2 flow rate has been investigated. Experimental results show that all these parameters have influences on etching rate and anisotropy, and RF power and chamber pressure are, respectively, the two dominant factors that affect etching rate and anisotropy. Etching rate can be increased at high RF power, optimal chamber pressure and optimal O 2 flow rate. Etching anisotropy can be improved by using high RF power, low chamber pressure, and low O 2 flow rate.

This paper presents a method for fabrication of flexible silicon sensor chips using temporary bonding, backside thinning, debonding, and flexible packaging. Flexibility of silicon chips requires ultrathin thickness, which imposes a challenge to debonding of thinned silicon chips from carrier wafers because of the fragility of silicon. To address this problem, temporary bonding using polypropylene carbonate (PPC), a heat-depolymerizable polymer material, as bonding adhesive is developed. PPC allows damage-free detachment of ultrathin silicon chips from carrier wafers by heating after backside thinning. The method is demonstrated and applied to the fabrication of silicon stress sensor chips with thickness down to $30~\mu \text{m}$ . The measurement results show that the ultrathin silicon chips have good flexibility and function well. The processes are optimized, and the detailed parameters are reported. The preliminary results demonstrate the feasibility of the method, and show its potential application in the fabrication of flexible ultrathin silicon sensors.

This paper presents design, fabrication, and high-frequency characterization of through-silicon-vias (TSVs) with benzocyclobutene (BCB) as the dielectric liner to exploit its low dielectric constant. Fabrication processes for BCB polymer liner TSVs are developed, and BCB-liner TSVs have been successfully fabricated in both low-resistivity silicon and high-resistivity silicon substrates for comparison. A de-embedding method that enables extraction of S-parameters from cascade TSV chains is developed based on the thru-reflect-line calibration algorithm, and the S-parameters of BCB-liner TSVs have been obtained from the measured transmission properties of cascade TSV chains with frequencies up to 25 GHz. Measurement results show that the BCB liner improves transmission properties of TSVs up to 10 GHz compared with SiO2-liner TSVs, and sub-strate resistivity dominates transmission properties for frequencies higher than 10 GHz.

BCB is emerging as an attractive bonding adhesive for wafer bonding in 3-D integration. Although the bonding strength of BCB is satisfactory with the assist of adhesion promoter, it is found that BCB suffers from interface delamination in harsh chemical or thermal conditions. This paper proposes, at chemical bond level, that the mechanism of interface delamination in KOH solution is attributed to the decomposition of Si O Si bonds at the interface between substrates and AP3000 adhesion promoter as a result of hydrolysis. Silicon dioxide and silicon nitride films with various densities of Si H and Si N bonds are prepared, and the bond densities are measured using infrared spectroscopy. The corresponding interface delamination rates of these films and BCB in KOH solution are measured, and the relations between the bond densities and the delamination rates are obtained for silicon dioxide and silicon nitride. It shows that the delamination rates decrease with the increase in the densities of Si O Si. These results demonstrate that the decomposition of Si O Si in KOH is the main reason for BCB delamination, and increase in the density of Si O Si improves the bonding strength.

Three-dimensional integration of microelectromechanical systems (MEMS) and CMOS is able to achieve hetero-integrated microsystems with high performance, small size, low cost, and multiple functions. This paper reports a 3-D integration method using wafer transfer technology and electroless Ni plating with a noncontact induction (ENPNI) technique. Wafer transfer technology based on adhesive bonding and wafer thinning allows stacked integration of MEMS on top of CMOS. To address the challenge in fabricating through-MEMS-vias (TMVs) with small diameters, ENPNI has been developed to fabricate Ni TMVs as both the mechanical supports for suspended MEMS and the electrical connects between MEMS and CMOS. High-density MEMS arrays and CMOS circuits are integrated to demonstrate the feasibility of the 3-D integration method, and thermal cycling and mechanical vibration are performed to evaluate the reliability. Experimental results show that the 3-D integration processes do not exert distinct influences on MEMS arrays and CMOS circuits, and the integrated systems have good yield, uniformity, and reliability. The capability of ENPNI in the fabrication of small TMVs enables 3-D integration of high-density MEMS arrays and CMOS circuits, such as micromirror arrays, infrared focal planes, acoustic sensor arrays, radiation sensor arrays, and so on. [2016-0056]

Using air gaps instead of conventional SiO2 liners as the isolators of through-silicon-vias (TSVs) has the potential for reducing thermal stresses and improving the thermomechanical reliability. This paper reports the thermal test results of newly developed air-gap TSVs with combined air-SiO2 insulators. Fabrication methods based on polymer sacrificial technology are reported. Thermal shock tests between −65 °C and +150 °C are performed, and the results show that the air-SiO2 liner TSVs are reliable over thermal shock with slight improvement in depletion capacitance and capacitance hysteresis. Chip curvatures caused by thermal expansion at high temperatures are measured, and it is found that the air gaps are able to mitigate plastic deformation of Cu plugs at high temperatures. These results indicate that the combined air-SiO2 insulators improve the electrical performance and the thermal stability of air-gap TSVs by isolating the organic residues originated from the sacrificial polymers, and the air-SiO2 liner TSVs have good structural integrity at high temperatures.

The use of air gaps instead of SiO2 as insulators for through-silicon vias (TSVs) has been demonstrated to reduce the thermal stresses and the TSV capacitance of a 3-D integrated system. However, since the Cu plug in air-gap TSVs lacks support and fixation at the sidewalls, the mechanical strength is a serious concern. This paper for the first time reports the mechanical and humidity reliabilities of air-gap TSVs. Reliability tests including free drop test, vibration test, and accelerated moisture test are performed, and the failure mechanisms are analyzed. The residual stresses in silicon substrates are also measured using micro-Raman Spectroscopy. Experimental results show that the premetal dielectric that acts as the only support for Cu plugs is the weak point causing mechanical reliability issues, and oxidation of Cu plugs at high moisture and high temperature is the main reason for humidity reliability problems. Multilayer bonding of TSV chips to constitute a 3-D system remarkably increases the mechanical and humidity reliabilities of air-gap TSVs because of the support and protection provided by the bonding chips.

This paper presents a method of achieving high sensitivity for silicon nanowire (SiNW) field-effect transistor (FET) pH sensor by operating the FETs in both capacitive amplification mode and differential amplification mode. The capacitive amplification is implemented by employing an inversed double-gate configuration that uses the electrode immersed in a solution well etched from the backside of the sensor chip as the top gate and the SiNW metal gate as the back gate. This enables the threshold voltages of the FETs to be amplified through the ratio of the top gate capacitance to the back gate capacitance. The differential amplification is achieved by a readout circuit chip that is vertically integrated with the sensor chip using flip-chip bonding. This allows the back gate to be controlled independently by the circuits, such that the differential amplification that is originally applicable to single-gate FETs can be applied to double-gate FETs. By operating the dual amplifications simultaneously, a sensitivity of 720.7 mV/pH has been achieved in the pH range of 4−10. Small deviations between the SiNW pH sensor and a commercial pH meter in measuring phosphate buffer saline, bovine serum, and tap water demonstrate the capability of the SiNW pH sensor in measuring practical samples.

Ternary Ge-Sb-Se chalcogenide glass (ChG) is emerging as an attractive material for fabricating micro optical devices due to the excellent optical properties. This paper reports the reactive ion etching (RIE) of ternary ChG films using CHF3 plasma for patterning microstructures. The influences of the etching parameters, including the ICP power, the chamber pressure, and the gas flow rate, on the etching rate and the anisotropy are investigated and optimized. Grass-like residues are found in high chamber pressure, and the formation mechanism is discussed. The results show that high RF power, low gas flow rate, and low chamber pressure are beneficial to achieving high etching rates and improving good anisotropy. The optimized etching parameters can be used as a baseline for patterning Ge-Sb-Se optical microstructures using reactive ion etching.

Hot Embossing method has been proved to be an effective way to fabricate chalcogenide microlens array for optical applications in this paper. A photoresist master mold is prepared using the traditional lithography and thermal reflow method, and the negative replica of the master mold is fabricated using polydimethylsiloxane, which serves as the stamp for hot embossing. After heated above the glass transition temperature of the chalcogenide glass with some pressure, patterns on the stamp can be transferred into the surface of the glass. Chalcogenide microlens array with desired parameters is fabricated and characterized.

Through-silicon-vias (TSVs) with air-gap insulators have the advantages of low capacitance and low thermal stress. This paper reports the design, fabrication, and characterization of new TSVs with combined air/SiO2 insulators. Sacrificial technologies based on heat decomposition of poly(propylene carbonate) and reactive ion etching of benzocyclobutene have been developed to fabricate uniform and high aspect-ratio air gaps. Air gaps with a thickness of 0.8 $\mu \text{m}$ and an aspect ratio of 62.5:1 have been successfully fabricated. Measurement results show that the SiO2 liner is able to eliminate the impacts of residues of the sacrificial polymers, and the TSVs with air/SiO2 have low capacitances and leakage currents at both room temperature and high temperature, constant minimum capacitance, and good temperature stability.

After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies. [2015-0158]

This paper reports a method of fabrication for small-feature-sized nickel (Ni) microbumps on gold (Au) using a newly developed technique called electroless Ni plating with noncontact induction (ENPNI). This technique, differing from conventional electroless Ni plating with contact induction (ENPCI), which directly connects an active metal with an inactive metal to induce Ni electrochemical reaction, is characterized by separation of the active metal and the target metal. The mechanism of ENPNI is interpreted by employing the electric-double layer theory, and some phenomena are explained by the proposed mechanism. Ni microbumps with a diameter of 3–6 $\mu \text{m}$ and a height of 3–4 $\mu \text{m}$ have been successfully fabricated using ENPNI. The resistance of the Ni microbumps is measured, and yield and uniformity are evaluated. By breaking the restriction of contact, ENPNI has the advantages of no need for pretreatment and contact induction, allowing fabrication of microbumps with small feature sizes for applications in which direct contact of an active induction metal is impossible.

A void-free bonding interface is critical to yield and reliability for high-quality wafer bonding. Although adhesive bonding using polymers as the bonding interface material is inherently able to restrain void-formation, for the wafers with uneven patterns like metal interconnects and alignment marks, void-free bonding is still challenging. This paper reports the void-formation in uncured and partially-cured benzocyclobutene (BCB) adhesive for bonding wafers with patterns. Experimental results show that uncured and partially-cured BCB has different behaviors in void-formation, and four types of voids, namely center voids, flower voids, micro voids, and floccules voids, are founded and their formation mechanisms are investigated. By optimizing bonding parameters for uncured BCB bonding, the center voids and flower voids are avoided and void-free bonding can be obtained. For partially-cured BCB, the micro voids and floccules voids tend to appear for uneven wafer surfaces. A reflow pretreatment at 140?C for 2h before curing process is beneficial to reducing the void areas.

Through-silicon vias (TSVs) with air gaps as the isolators have been developed to reduce the TSV capacitance and to solve the reliability problems associated with thermomechanical stresses. This paper reports the reliability assessment of the air-gap TSVs by measuring the $C$ – $V$ , $I$ – $V$ , and resistance of the TSVs in terms of thermal and electrical stresses with a focus on thermal shock, temperature variations, and voltage ramps. Thermal shock tests are performed to evaluate the insulation capability and the thermomechanical stability of the air gaps. Temperature variations are implemented to investigate the influences of high temperatures on the electrical characteristics of the air-gap TSVs. Voltage ramp tests are carried out, and the time-dependent dielectric breakdown is obtained to evaluate the integrity of the air gaps and the intrinsic barrier capability. The preliminary results show that the air-gap TSVs have good thermal stability, excellent dielectric property, and satisfactory structure and barrier stability.

Silicon nanowire (SNW) field-effect transistors (FETs) have proven an emerging highly sensitive bio/chemical sensor due to their huge surface-to-volume ratios. However, fabrication of SNWs with both high output and low cost is still challenging. This paper presents a new fabrication method using sidewall mask technology. By depositing a conformal thin film on a sacrificial pattern and removing the surface film, the vertical part of the film on the pattern sidewall is left as a mask, of which the feature size is determined by the film thickness that can be readily controlled in nanometer regime. This allows wafer-scale, high output, and low cost fabrication of SNWs without need of advanced lithography facilities. The SNWs are operated in a FET configuration by applying gate voltages via a reference electrode immersed into solutions. Demonstrated as a pH sensor, the SNW FETs achieve sensitivity as high as 54.5 mV/pH for pH values from 1 to 12, approaching the theoretical Nernstian limit.

Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the potential for reducing the TSV capacitances and the thermal expansion stresses. This paper reports the assessments of BCB-liner TSVs with respect to thermal and electrical properties. The C-V and I-V characteristics are measured at room temperature and at an elevated temperature as high as 125°C to characterize the electrical properties of capacitance and leakage current at different temperatures. Some C-V and I-V features associated with BCB-liners are discussed and the mechanisms are analyzed. Thermal cycling between -65°C and 150°C is performed, and the C-V and I-V characteristics are measured before and after thermal cycling to evaluate the thermomechanical stability of the BCB-liners, and the results show that the C-V and I-V properties are improved after thermal cycling. These preliminary results on the electrical and thermal properties of BCB-liner TSVs show that they have good thermal stability.

This paper reports the development of a highly-sensitive and ultra-thin silicon stress sensor chip (UTSC) and its applications for wearable sensors. Stress sensor chips are fabricated using CMOS technology, and after dicing the individual chips are reconfigured into a virtual wafer on a carrier wafer using temporary adhesive bonding. The reconfigured wafer is then thinned using mechanical grinding, polishing, and wet etching. After thinning, the sensor chips with thickness of 35 μm are laminated to a thin Kapton PI film, followed by de-bonding to separate the carrier wafer. Measurement results show that the UTSC is able to comply with curved surfaces, and the sensitivity is around 70 times that of metal strain gauge. The specifications of the UTSC are characterized in terms of linearity, repeatability, hysteresis, and zero drift. The UTSCs are demonstrated to measure human pulses on wrist and orthodontic forces of invisible aligners for dental treatment. The preliminary results show that the reconfigured method is applicable to thinning individual chips, and the UTSCs are flexible and sensitive enough for measurement of stress and strain on curved surfaces on human bodies.

Pattern transfer on structured surfaces is still a technical challenge in MEMS fabrication due to the accumulation of photoresist at the structure base and the discontinuity at the structure opening. This paper reports a planarization method which employs a two-step polymer spin-coating to cap the structures to facilitate pattern transfer on structured surfaces. The first spin-coating uses heat-depolymerizable poly (propylene carbonate) (PPC) to either partially fill or completely intersect the structures, and the following spin-coating uses polyimide (PI) to form a complete capping film on the structured surfaces. The thermal decomposable feature of PPC allows it to decompose as a sacrificial layer during PI curing, leaving only PI films on the structured surfaces after the two-step coating. High topography surfaces with deep holes with diameter of 25 μm, long trenches with length of 500 μm, and large cavities with width of 100 μm, have been well planarized using the proposed method. Subsequent photolithography verifies that photoresist can be well applied onto the planarized surfaces, and the pattern transfer results are satisfactory. Silicon dioxide deposited using plasma enhanced chemical vapor deposition (PECVD) and aluminum deposited using sputtering are also demonstrated on planarized surfaces. The preliminary results demonstrate the feasibility of planarization of high topography surfaces using the two-step coating method.

Due to the flowability of benzocyclobutene (BCB) and the unavoidable shear components of the bonding force applied by bonding facilities, it is quite challenging to achieve void-free BCB adhesive bonding with simultaneous high post-bonding alignment accuracy. To solve this problem, this paper reports a compensation method for alignment errors to achieve simultaneous void-free and accurate wafer bonding using soft-baked BCB. By characterizing the wafer shift induced bonding force, it is found that the wafer shift is a systematic error associate with the bonders but independent of the wafers. Upon this investigation, a compensation method presetting a pre-bonding alignment shift opposite to the post-bonding shift is proposed to compensate the bonding induced wafer shift. Using this method, void-free bonding with soft-baked BCB has been achieved, and the alignment errors are improved significantly from around 35---40 μm to around 3 μm. Test results show that the average bonding strength of soft-baked BCB is about 26.4 % higher than that of partially-cured BCB. The preliminary results demonstrate the efficacy of the proposed compensation method, which has potential to improve the alignment accuracy of BCB bonding for three-dimensional integration, MEMS, and microsensors.

Open microfluidics is an emerging field of bio/medical applications that need direct energy/matter exchange between microfluids and environment. This paper presents the design, simulation, fabrication, and test of a microfluidic chip for a water-in-oil (WiO) two-phase flow in closed-open-closed microchannels. The chip, fabricated from PDMS using soft lithography, consists of a flow-focusing structure for WiO droplet generation and a long closed-open-closed channel for droplet flow. A negative pressure applied to the end of the channel is used as the driving force for WiO droplets to flow through the open channel. It is found that the negative pressure that is capable of driving a steady flow for a given flow rate, without overflow and air suction, falls into a pressure range instead of being an exact value. The mechanism for the pressure range is investigated theoretically and experimentally and is attributed to the surface tension. Yeast cells have been incorporated in the droplets, and the successful flow through the open channels verifies the function of the chips.

This paper reports the development of a hot embossing method for fabricating chalcogenide microlens arrays using soft polydimethylsiloxane (PDMS) stamps. The stamps are formed by molding PDMS on photoresist masters fabricated with sphere segments by thermal reflow. Upon proper temperatures, the chalcogenide glass softens and is embossed using PDMS stamps with low pressure. Void defects at the center and at the side of microlenses are found, and the mechanisms for the void formation are investigated and verified. The hot embossing parameters including pressure, temperature, embossing time, and the thicknesses of the PDMS stamps are optimized. A 400 × 400 microlens array with uniform profiles, smooth surface roughness, and good roundness have been successfully fabricated on both chalcogenide thin films and bulk wafers. The preliminary results demonstrate the feasibility of using hot embossing with soft PDMS stamps as a simple and low cost method to fabricate chalcogenide microlens arrays.

Using air-gaps to replace conventional silicon dioxide as the insulators of through-silicon-vias (TSVs) has the possibility to improve the electrical performance and some thermal reliability issues of TSVs. This paper reports the implementation of TSVs with air-gap insulators by developing a polymer sacrificial technology. The sacrificial technology and the key fabrication processes are investigated in detail, including spin-coating of poly propylene carbonate (PPC) on the sidewalls of blind vias, copper chemical-mechanical polishing, PPC grinding, and PPC pyrolysis to form air-gaps. To address the technical challenge in coating thin and conformal PPC sacrificial claddings in blind vias, a vacuum-assisted solvent refilling technique is developed. Air-gap TSVs are successfully fabricated and the electrical performances are characterized. The accumulation capacitance of the air-gap TSVs is 48 fF, and the leakage current is as low as 1.22 pA at bias voltage of 20 V. Finite element simulation shows that air-gaps are able to reduce thermal stresses. The preliminary results demonstrate the feasibility of the sacrificial technology and the good electrical performance of air-gap TSVs.

Through-silicon-vias (TSVs) using benzocyclobutene (BCB) as insulation layers (liners) are developed and the reliability related issues with regard to mechanical and electrical aspects are investigated. The BCB TSVs are fabricated using deep etching of annular trenches on a substrate, BCB cladding forming in the deep trenches, selective etching of the silicon posts in BCB claddings, and electroplating of copper plugs. The insulation capability and the configuration stability of BCB liners are evaluated by performing a thermal shock test and comparing the leakage currents before and after thermal shock. The results show that the BCB insulation capability does not change distinctly after thermal shock. Auger electronic spectroscopy (AES) is used to characterize copper diffusion through BCB thin films after high temperature treatment, and it is found that BCB is able to prevent copper diffusion at temperatures as high as 350 °C. Finite element analysis is performed to understand the thermal stress behaviors of BCB TSVs, and the simulation results show that BCB liners are able to reduce the thermal induced stresses in substrates, but increase the axial thermal expansion of copper plugs.

Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This paper reports the development of a low capacitance TSVs by replacing silicon dioxide insulation layers (liners) with benzocyclobutene (BCB) polymer. The BCB liner TSVs are fabricated by etching deep annular trenches on substrates, void-free filling the trenches with BCB polymer, selective etching the silicon post in the annular trenches, and filling the via with copper. Key fabrication processes including void-free BCB polymer filling in deep trenches, BCB chemical mechanical planarization, and selective etching of silicon post to BCB are developed. TSVs with BCB liners are successfully fabricated and the electrical performance is measured. The measurement results show that the capacitance of the BCB liner TSVs is around 42 fF, and the leakage currents to substrates and to neighboring TSVs are 2.2 pA and 1.1 pA at 10 V voltage, respectively. These preliminary results demonstrate the feasibility of the proposed fabrication technology and the efficacy of BCB liners in reducing TSV capacitance.

A laser-assisted chemical vapor deposition (LCVD) method has been developed for in situ synthesis of carbon nanotube (CNT) films on suspended microstructures. Focused laser beams are used to heat locally the suspended microstructures with low thermal mass and low thermal dissipation to high temperatures for localized CNT growth. Other substrate areas than the microstructures remain at low temperatures, preventing the devices on the substrate from being destroyed by high temperatures. The synthesizing parameters and the influences on CNT morphology and structures are systematically investigated and optimized, and solutions for uniform temperature distribution are proposed. Upon optimization, uniform, localized, and rapid growth of CNT synthesis has been achieved on suspended microstructures, and aligned CNTs with length and uniformity comparable to conventional hot-wall CVD have been successfully obtained. The experimental results show LCVD is a promising technology for in situ and localized synthesis of CNT films on suspended microstructures for CNT-CMOS (complementary metal oxide semiconductor) integration.

Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO2 liner TSVs. The leakage current to the substrate is 3 ×10-13 A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance.

Polymer insulation layers (liners) have several potential advantages in terms of capacitance and reliability over conventional silicon dioxide for through-silicon-via (TSV) applications. This paper reports the development and measurement results of a TSV using poly (propylene carbonate) (PPC) polymer as the insulation layers. To address the challenge in coating thin and uniform PPC liners on the sidewalls of high aspect-ratio vias, a spin-on technique using vacuum treatment and solvent refill is developed to prevent formation of air bubbles in the vias, and using this technique circular vias with aspect-ratio as high as 9:1 have been coated with uniform PPC layers. Based on these results, TSVs with thick PPC polymer liners have been fabricated and the capacitance and the current leakage are measured. Thanks to the relatively large thickness and the low dielectric constant of PPC liners, the TSV capacitance density is about 2.45nF/cm^2 and the leakage current is around 40nA/cm^2 at 5V voltage, indicating that replacing silicon dioxide with PPC as liners considerably reduces TSV capacitance. The preliminary results demonstrate the feasibility of fabrication of high aspect ratio and low capacitance TSVs with polymer liners.

Detection of trace explosives is still a challenging task because of the extremely low vapor concentrations. This paper reports a new microcalorimeter for detection of trace explosives with low detection limit and fast detection rate. The microcalorimeter consists of a suspended micromembrane with integrated heaters and thermistors and a carbon nanotube (CNT) interface layer in-situ synthesized on the membrane surface. Due to the large surface areas, the CNT interface layer improves adsorption to target chemical molecules. By operating the microcalorimeter in differential scanning calorimetry mode and differential thermal analysis mode, trace chemical detection is achieved through heating the adsorbed chemicals to deflagration and measuring the induced thermal response features and the total heat. The microcalorimeter is verified by explosive detection, and an equivalent limit of detection of 2.6 pg has been achieved by extrapolating the measurement results. Theoretically, detection is distinguishable upon 10-s fast exposure to saturated explosive vapors. These preliminary results demonstrate the ability of the microcalorimeter in detection of trace energetic chemicals.

This paper reports a cell trapping and patterning method using dielectric-pattern-assisted negative dielectrophoresis (dnDEP) that can achieve high-density cell arrays and complicated cell patterns. The dnDEP device consists of two planar metal electrodes and a patterned dielectric layer sandwiched in-between. The dielectric patterns generate non-uniform electric fields when an ac voltage is applied on the two electrodes, and the interaction of polarizable cells and the non-uniform electric fields imposes negative DEP forces on the cells, pushing them to the patterns in the dielectric layer. Using this dnDEP device, human lymphoma cells were successfully patterned in high-density microwell arrays and stellate structures. Thanks to the three-dimensional configuration and the small distance between the electrodes, cell trapping and patterning can be implemented with a voltage of 10 V. This dnDEP device has the advantages of simple configuration, low actuating voltage, and the compatibility with high conductivity physiological media for cell culturing.

This paper reports a chemical sensor that consists of a suspended microcantilever and a carbon nanotube (CNT) network that is in situ synthesized on the microcantilever. The in situ synthesis achieves minimized thermal resistance of the interface between the CNTs and the microcantilever, which together with the low thermal mass and the high thermal conductivity allows the sensor to operate in microcalorimeter mode. By heating the CNT networks with an integrated heater, the explosive vapors adsorbed on the CNT surfaces are ignited to deflagration, which releases extra heat to deflect the microcantilever and thus changes the resistance of an integrated piezoresistor. This thermal-mechanical coupling transduction mechanism bridges the heat changes on the CNT networks and the mechanical deflection of the microcantilever. The large surface to volume ratio of CNTs enables fast adsorption of the chemical sensor to explosive vapors and improved equivalent limit of detection (LOD). An equivalent LOD of 2.4 pg is achieved for TNT detection, and run-to-run repeatability and device-to-device reproducibility are better than 4% and 10%. The preliminary results demonstrate the feasibility of development of sensitive CNT chemical sensors using in situ synthesized CNT networks and thermal-mechanical coupling transduction mechanism.

A technical challenge in fabrication of ultra-thin sensor chip (UTSC) is to keep chip integrity in debonding the ultra-thin chips from grinding facilities. This paper presents a new debonding method by utilizing a thermally decomposable polypropylene carbonate (PPC), as the temporary bonding adhesive. Because PPC can readily decompose at relatively low temperature, this method can maintain the chip integrity even the chips have a thickness of tens of microns. UTSCs with thickness of 30μm have been achieved using this method, and stress sensors have been developed to verify the performance of UTSC. The experimental results show that the proposed method is able to fabricate UTSC with good flexibility and characterizations, demonstrating the newly proposed method an enabling technology for fabrication of sensors for flexible and wearable applications.

In this paper, a novel manufacturing scheme based on heat-depolymerizable material and thermosetting material is proposed to achieve high performance through silicon vias (TSVs) with porous polymer insulation liners. In order to strengthen the mechanical reliability and guarantee the low capacitance and low thermal expansion stress of TSVs, we come up with the novel TSVs with porous polymer insulation liners. And we present a manufacturing scheme for the porous polymer insulation liners. The polymer adopted in the manufacturing scheme is the mixture polymer of heat-depolymerizable material Polyimide (PPC) and thermosetting material Polyimide (PI). To address the challenge in fabrication of porous polymer liners in high aspect-ratio TSVs, we have adopted a vacuum-assisted spin-coating technology for filling the mixture polymer (PPC&PI) in high aspect-ratio annular trenches. Finally, through initial pre-cure and eventual pyrolysis, the porous structure can be achieved.

We present a monolithic integration of multiple sensors that have various structures and different packages. The multi sensors include an electrical field sensor (EFS) and accelerometers in a vacuum package and pressure, humidity, temperature sensors with direct contact with environment. To conduct the electrical signals from the vacuum package, three-dimensional (3-D) integration is implemented with a silicon interposer with through-silicon-vias (TSVs). The configuration of the multi sensor system, the co-design and co-fabrication, and packaging schemes are presented.

Through-Silicon-Vias (TSVs) with polymer liners have potential improved electrical and mechanical reliability for three-dimensional (3D) packaging/integration applications. To address the challenge in fabrication of polymer liners in high aspect-ratio TSVs, we have developed a vacuum-assisted spin-coating technology for filling benzocyclobutene (BCB) polymer in high aspect-ratio annular trenches. The newly developed spin-coating technology employs spin-coating twice and vacuum treatment after each coating. The vacuum treatment removes the bubbles at the trench bottom trapped during spin-coating and curing, and facilities the formation of void-free BCB filling. The influences of the BCB viscosities and the spin-coating parameters on the filling ability are evaluated, and upon optimization annular trenches with aspect-ratio as high as 22 have been successfully filled with no void formation, thin overburden, and slight dishing. This method is also applicable to trench filling using polymers with similar properties.

A silicon piezoresistive stress sensor is developed to measure the three components of the orthodontic forces of a tooth in invisible aligners. The stress sensor chip consists of multiple piezoresistor rosettes, and is fixed on the tooth surface to measure the orthodontic force induced stresses. An inverse problem algorithm is established to reconstruct the orthodontic forces of the tooth from the measured stresses. A key thinning process is developed using chemical-mechanical polishing to thin the sensor chip from 650 to 100 , such that it can be accommodated to the limited space between the aligner and the tooth, without much influence on the orthodontic force. The ultra-thin thickness enables the sensor chip to be compliance with tooth deformation, and improves the stress measurement sensitivity as much as 40 times, making it capable of measuring small orthodontic force. The sensor design, fabrication, orthodontic stress measurement, and force reconstruction are given in details, and the experimental results demonstrate the feasibility of using miniaturized and ultra-thin sensors to determine the in vitro orthodontic forces.

This paper reports a novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment. The key unit process steps, including template fabrication, chip edge definition, C2W alignment and bonding, are investigated. To demonstrate this C2W approach, benzocyclobutene (BCB) and Cu are selected as the starting materials for template and bonding, respectively. Wafers with Cu daisy chains are fabricated for both the chip and host wafer. Individual chips are produced by a 2-step process: defining the chip edges and dicing. All individual chips are aligned to the host wafer with a BCB template, followed by a wafer-level Cu-Cu bonding process. An alignment accuracy of approximately [email protected] is achieved and a good Cu-Cu bond interface is observed with Cu grain-growth across the bonding interface. This C2W 3D integration approach has the potential for low cost and high throughput fabrication of multi-layer high-performance 3D systems.

A microbridge based calorimetric sensor is developed for the detection of trace energetic substances by measuring their characteristic temperature change in thermal reactions. The micro-calorimeter is mainly a suspending microbridge made of silicon dioxide (SiO2) and integrated with heating and detecting resistors. It is fabricated based on silicon-on-insulator (SOI) wafers using a front-side releasing method, which is simple, efficient and high-yielding. The tiny microbridge is with an extremely low dimension and achieves low thermal capacity, allows small temperature changes induced by chemical reactions detectable. A limit of detection of sub-100 pg is demonstrated for trinitrotoluene (TNT) by measuring the endothermic and exothermic reactions when heating the preconcentrated TNT to the deflagrating temperature, indicating the ability of the sensors in energetic chemical detection.

This paper presents the experimental and theoretical investigation of the thermal stress development in the C2W 3D integration with template alignment and the impact of fabrication parameters on the thermal stress. The experimental approach is accompanied with an optical profilometer, while the theoretical study is based on COMSOL FEM analysis. It is found that the thermal stress is primarily induced in the polymer hard curing process, and is accumulated within the cooling process due to the mismatch of coefficients of thermal expansion (CTE) with substrate. The thermal stress highly depends on the polymer thickness and the treatment temperature, and could be partially released by polymer etching. The measurement and simulation results indicate that the template alignment technology is compatible with semiconductor fabrication by optimizing the fabrication parameters. The feasibility of C2W 3D integration with template alignment is furthered demonstrated.

Thermal management is one of the critical challenges in three-dimensional (3D) integration. As the polymer bonding adhesive is the major source of the internal thermal resistance in 3D integration, this paper reports an approach to increase the thermal conductivity of the bonding adhesive benzocyclobutene (BCB) by loading carbon nanotubes (CNTs). By exploiting the aromatic property of BCB, an ultrasonication and mechanical stirring assisted non-covalent dispersion method is developed to disseminate CNTs with concentrations ranging from 0.25% to 2% to form BCB-CNT composites. The effects of ultrasonication and mechanical stirring on CNT dispersion are experimentally investigated, and the electrical properties, the thermal diffusivity, and the bonding strength of BCB-CNT composites are characterized. The results show that ultrasonication in conjunction with mechanical stirring can significantly improves the CNT dispersion results, and an 80% improvement in the thermal conductivity is achieved for BCB by loading CNTs. The bonding strength of BCB-CNT composites, though varies with CNT concentrations, are improved compared with pure BCB for CNT concentrations less than 1.75%.

This paper reports a method for measuring the heat capacity of as-grown carbon nanotubes (CNTs) using a microcalorimeter. The microcalorimeter consists of a double-layer suspended silicon dioxide microstructure and two silicon resistors sandwiched in-between the silicon dioxide layers. CNTs for heat capacity measurement are locally synthesized on the surface of the microstructure using laser-assisted chemical vapor deposition. The CNTs and the microcalorimeter are heated to a high temperature with a silicon resistor, and the temperature of the microcalorimeter with CNTs is measured with using the other silicon resistor. The heat capacity of the CNTs is obtained by dividing the measured effective heating power by the rate of temperature increase. The suspended configuration and the low thermal conductivity of silicon dioxide achieve low thermal dissipation, which together with the minute thermal capacity enable significant temperature changes. Using this sensitive microcalorimeter, the heat capacity of as-grown CNTs, 6-14 nJ/K from 340 to 440 K, is measured in-situ without the need of CNT transfer and pretreatment, avoiding damage to the CNT samples. This microcalorimeter is also applicable to in-situ measurement of structure-related thermal properties of porous materials.