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Wurtzite AlN films with high Fe concentrations were deposited on Si(100) substrates using radio-frequency sputtering, and the growth process was investigated. X-Ray diffraction (XRD) analysis with parallel incident X-rays showed that a thick film (∼2.5 μm) had a non-polar a-axis orientation, similar to the films deposited on SiO2 glass substrates. Through powder XRD analysis, it was found that non-wurtzite fine crystals and/or amorphous materials formed during the initial stage of deposition, followed by wurtzite nucleation with various orientations of the axes, such as a, m, and r orientations. The XRD results also implied that the a-axis-oriented regions drastically increased with increasing film thickness. Scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy analyses suggested that one of the candidates for the non-wurtzite fine crystalline material was γ-Al2O3. STEM analysis also demonstrated that a-axis-oriented single-crystal grains grew from randomly oriented small wurtzite grains that increased in diameter with increasing deposition time. Al K-edge X-ray absorption near-edge structure results suggested that the electronic structure in the polar c-axis direction of wurtzite lying in the film plane developed with deposition time, thereby further supporting the findings of the XRD and STEM analyses.

This paper describes the demonstration of a low loss substrate (laminated glass) for high-frequency transmission using a dry film build-up material with low loss tangent (Df). This paper also evaluates filter characteristics and dielectric characteristics of the substrate in the mm-Wave band. The advanced low loss dry film build-up material was newly developed, and applicable to high frequency transmission. This material has a Df of 0.0025 at 10 GHz and also exhibits excellent adhesion and electrical reliability required for advanced dielectric materials. In addition, glass was used as a core material in this paper because of its excellent signal transmission characteristics compared to silicon wafers or organic substrates. To demonstrate the benefit of low loss materials for high frequency transmission, passive components for high frequency filter substrates were fabricated using - 6-inch square thin (0.2mm) glass panel with various build-up materials (Material A with a Df of 0.0025, and Material B with a Df 0.0042 at 10 GHz) laminated. Copper wiring patterns on the dielectric layers were fabricated by a semi-additive process (SAP). Circuit patterns with low pass filters and band pass filters were also fabricated. First, transmission characteristics and characteristic impedances were measured to check the electrical performance. The measured lowest transmission loss of < 1.43 dB at 39 GHz were achieved when Material A was applied as the build-up material. Second, biased-highly accelerated stress test (bHAST) was conducted to evaluate the reliability performance of the substrates with two build-up materials, Material A and a conventional material. The test condition was based on the JEDEC level 2 standard. The substrate with Material A retained good insulation properties over 300 hours of bHAST treatment, demonstrating its excellent insulating performance. In summary, Material A has been shown in this paper to exhibit reduced transmission loss in high-frequency filter substrates at millimeter wave frequencies.

This paper presents an innovative process technology in solder resist (SR) thinning to form multi-stepped SR structures. The resist thinning (RT) process can thin down SR layer highly uniformly at a large panel scale. The RT process is also capable of SR patterning by combined with photolithography process to enable selective SR thinning. This paper first discusses the process mechanism and studies impact of process parameters. Comparison studies of the RT process against a standard development process were conducted to demonstrate uniform SR thickness reduction by the RT process. Additionally, variety of unique SR structures were demonstrated using the RT process to illustrate potential applications of the process to variety of packaging substrates, such as ultra-thin substrates, high-density substrates, and multi-chip module substrates.

This paper describes the development of a novel dry film-type dielectric material with low loss tangent (D f ) and the demonstration of a low-loss filter substrate using the dielectric material for high-frequency transmission applications. This paper also presents the evaluation results of the small filter characteristics of the substrate in the 28 GHz and 39 GHz 5G millimeter-wave (mmWave) band. We have recently developed a dry film dielectric material with outstanding electrical properties and excellent mechanical properties (Material P). This new material is based on polyphenylene ether (PPE) that has extremely low D f . PPE is commonly known as a thermoplastic polymer, henceforth a new chemical design was applied to modify the polymer structure into a thermosetting polymer. The new dielectric material can be processed at a low temperature about 200°C and is compatible to the standard substrate manufacturing processes, such as semi additive process (SAP). Material characterization revealed that D k /D f of Material P is 3.1 /0.0013 at 10 GHz, and glass transition temperature (T g ) is 200°C. In this work, RF filter performance of the Material P was characterized to demonstrate the benefit of the low loss material. As the reference, the performance of epoxy dielectric was additionally characterized and compared. Electrical characterization of the filter structures showed low transmission losses < 1.0 dB at 28 GHz and < 0.8 dB at 39 GHz with Material P, verifying applicability of the material for high frequency applications.

With the tremendous advances and increasing demand in 5G communications, the low-loss performance of RF device components becomes more critical. Two parameters that have significant impact on the low-loss RF performance are lower circuit conductor loss and dielectric loss of the build-up materials. Therefore, this study is focused on the loss tangent (D f ) of the dielectric build-up material and demonstration of its electrical reliability with a low-loss substrate for high-frequency transmission. This newly developed advanced low-loss dry film build-up material exhibits a D f values of < 0.003 at 39 GHz and is applicable to high frequency transmission. This build-up material also exhibits excellent electrical reliability required for advanced dielectric materials. For evaluation of the filter characteristics in the mm Wave band, a substrate with filter circuit structures was fabricated using the low loss dielectric material. Transmission characteristics of the filters were measured and demonstrated to have a minimum transmission loss of less than 1.18 dB at 39 GHz.

Assuming that the 0.6-&mu, m silicon-on-insulator (SOI) complementary metal&ndash, oxide&ndash, semiconductor (CMOS) technology, different Si-based temperature sensors such as metal-oxide-semiconductor field-effect transistor (MOSFET) (n-channel and p-channel), pn-junction diode (with p-body doping and without doping), and resistors (n+ or p+ single crystalline Si and n+ polycrystalline Si) were designed and characterized for its possible use in 1-THz antenna-coupled bolometers. The use of a half-wave dipole antenna connected to the heater end was assumed, which limited the integrated temperature sensor/heater area to be 15 &times, 15 &micro, m. Our main focus was to evaluate the performances of the temperature sensor/heater part, and the optical coupling between the incident light and heater via an antenna was not included in the evaluation. The electrothermal feedback (ETF) effect due to the bias current was considered in the performance estimation. A comparative analysis of various SOI bolometers revealed the largest responsivity (Rv) of 5.16 kV/W for the n-channel MOSFET bolometer although the negative ETF in MOSFET reduced the Rv. The noise measurement of the n-channel MOSFET showed the NEP of 245 pW/Hz1/2, which was more than one order of magnitude smaller than that of the n+ polycrystalline Si resistive bolometer (6.59 nW/Hz1/2). The present result suggests that the n-channel MOSFET can be a promising detector for THz applications.

In this paper, we report an advanced low-loss dry film build-up material applicable to high-frequency transmission, and evaluation of filter characteristics and dielectric characteristics in the mmWave band. The wireless communication standard is evolving from 5G to beyond 5G, and accordingly, it is critical to lower the loss tangent (Df) of build-up materials to enable high-speed transmission in signal paths. However, for high frequency filter applications, conventional materials such as epoxy and polyimide type build-up materials induce high insertion loss in the passband. This paper therefore introduces a lower-Df dry film build-up material (Material A) and investigates transmission characteristics of the same. To evaluate the insulation reliability and electrical performance of the material, test vehicles with precise copper patterns are designed and fabricated with a semi-additive patterning process (SAP) using the Material A. Each test board was fabricated to evaluate the insulation reliability and electrical performance of the material. By applying the Material A for SAP, over 5N/cm high peeling strength is achieved despite of the smooth surface. The material demonstrates an excellent insulation reliability between copper lines and between copper layers, specifically 300 hours of bHAST attributed to its low chlorine impurities. The dielectric property Df of the material is 0.0025 at 10 GHz. The electrical performance of lowpass filters and bandpass filters are measured by electrical analysis using microwave network analyzers system. These test boards demonstrate to achieve a low transmission loss of less than 1 dB at 28 GHz as a lowpass filter, and 1.05 dB at 28 GHz and 1.18 dB at 39 GHz as a bandpass filter. As a result of this excellent low transmission loss, this material has promising application potential for millimeter wave applications.

In this study, the optimum density scaling factors of phantom materials for a commercially available three‐dimensional (3D) dose verification system (Delta4) were investigated in order to improve the accuracy of the calculated dose distributions in the phantom materials. At field sizes of 10 × 10 and 5 × 5 cm2 with the same geometry, tissue‐phantom ratios (TPRs) in water, polymethyl methacrylate (PMMA), and Plastic Water Diagnostic Therapy (PWDT) were measured, and TPRs in various density scaling factors of water were calculated by Monte Carlo simulation, Adaptive Convolve (AdC, Pinnacle3), Collapsed Cone Convolution (CCC, RayStation), and AcurosXB (AXB, Eclipse). Effective linear attenuation coefficients (μ eff) were obtained from the TPRs. The ratios of μ eff in phantom and water ((μ eff)pl,water) were compared between the measurements and calculations. For each phantom material, the density scaling factor proposed in this study (DSF) was set to be the value providing a match between the calculated and measured (μ eff)pl,water. The optimum density scaling factor was verified through the comparison of the dose distributions measured by Delta4 and calculated with three different density scaling factors: the nominal physical density (PD), nominal relative electron density (ED), and DSF. Three plans were used for the verifications: a static field of 10 × 10 cm2 and two intensity modulated radiation therapy (IMRT) treatment plans. DSF were determined to be 1.13 for PMMA and 0.98 for PWDT. DSF for PMMA showed good agreement for AdC and CCC with 6 MV x ray, and AdC for 10 MV x ray. DSF for PWDT showed good agreement regardless of the dose calculation algorithms and x‐ray energy. DSF can be considered one of the references for the density scaling factor of Delta4 phantom materials and may help improve the accuracy of the IMRT dose verification using Delta4.

This paper describes the first demonstration of 20- $\mu \text{m}$ -diameter microvias etched through a 5- $\mu \text{m}$ -thin build-up polymer dielectric, Ajinomoto build-up film GX92, using ozone gas as a massively parallel etch process. This report begins with the demonstration of effective etching of polymer dielectric materials with the ozone gas process. With the use of proper etching masks such as metals or photoresist (PR) layers with openings on top of the dielectric layer, microvias were successfully formed in the dielectric layer. The effect of the different mask materials on the microvia etching rates and via diameters was examined. Microvias with 20 $\mu \text{m}$ diameter and 5 $\mu \text{m}$ depth were achieved with the PR mask with 15- $\mu \text{m}$ openings. After desmear cleaning process, microvias were metallized by electroless and electrolytic copper-plating processes. Thermal shock test between −55°C and 125 °C was applied to the daisy-chain structures to evaluate the microvia reliability made by ozone etching processes. There was no microvia failure up to 5000 cycles to confirm the reliable interconnection of the formed microvias. The microvia formation process using ozone can create a large number of microvias at once, which is beneficial for large panel application.

This paper presents the modeling, design, fabrication, and characterization of an innovative and miniaturized thin-film bandpass filter with coupled spiral structures in ultrathin glass substrates (30– $100~\mu \text{m}$ ). This filter is demonstrated for two applications: 3-D integrated passive devices and embedded thinfilm filters in RF modules. A compact filter design was achieved through an integrated resonant structure that effectively utilizes the inductive and capacitive coupling between metal layers on either side of an ultrathin glass substrate or organic build-up layer. The designed filters (layout area $150~\mu \text{m}$ device thickness) were fabricated on a 30- $\mu \text{m}$ -thin glass substrate using a panel-based low-cost approach with double-side thin-film wiring processes. The effect of process variations on the performance of the proposed structures was also studied. Furthermore, an improved WLAN filter is designed and demonstrated by employing specific structural modifications. The measured frequency response of the filters shows good model-to-hardware correlation, with very low insertion loss (0.6 dB) in the passband, and high adjacent-band rejection (>25 dB).

To improve the reliability of silicon carbide (SiC) electronic power devices, the characteristics of various kinds of crystal defects should be precisely understood. Of particular importance is understanding the correlation between the surface morphology and the near surface dislocations. In order to analyze the dislocations near the surface of 4H-SiC wafers, a dislocation analysis protocol has been developed. This protocol consists of the following process: (1) inspection of surface defects using low energy scanning electron microscopy (LESEM), (2) identification of small and shallow etch pits using KOH low temperature etching, (3) classification of etch pits using LESEM, (4) specimen preparation of several hundred nanometer thick sample using the in-situ focused ion beam micro-sampling® technique, (5) crystallographic analysis using the selected diffraction mode of the scanning transmission electron microscope (STEM), and (6) determination of the Burgers vector using multi-directional STEM (MD-STEM). The results show a correlation between the triangular terrace shaped surface defects and an hexagonal etch pit arising from threading dislocations, linear shaped surface defects and elliptical shaped etch pits arising from basal plane dislocations. Through the observation of the sample from two orthogonal directions via the MD-STEM technique, a basal plane dislocation is found to dissociate into an extended dislocation bound by two partial dislocations. A protocol developed and presented in this paper enables one to correlate near surface defects of a 4H-SiC wafer with the root cause dislocations giving rise to those surface defects.

This paper reports on one of the first demonstrations of the formation and metallization of 2–5- $\mu \text{m}$ lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, without using chemical mechanical planarization. The trenches and vias in 8–15- $\mu \text{m}$ -thick dry-film dielectrics were formed by 308-nm excimer laser ablation, followed by the metallization of the trenches and vias by copper electrodeposition. A low-cost planarization process was used to remove the copper overburden with a surface planer tool. Using an optimized set of materials and processes, multilayer redistribution layers with 2– $5~\mu \text{m}$ trenches and vias were successfully demonstrated. Although thin film processes on silicon wafers have been able to achieve 40- $\mu \text{m}$ I/O pitch for interposers, the materials and processes integrated in this paper are scalable to large panel fabrication at much higher throughput, for interposers and high-density fan-out packaging at lower cost and higher performance than silicon interposers.

The recently developed multi directional scanning transmission electron microscopy (MD-STEM) technique has been applied to exactly determine the Burgers vector (b) and dislocation vector (u) of a threading mixed dislocation in a silicon carbide (SiC) as-epitaxial wafer. This technique utilizes repeated focused ion beam (FIB) milling and STEM observation of the same dislocation from three orthogonal directions (cross-section, plan-view, cross-section). Cross section STEM observation in the [1-100] viewing direction showed that the burgers vector have a and c components. Subsequent plan view STEM observation in the [000-1] direction indicated that the b=[u -2uuw] (u≠0 and w≠0). Final cross section STEM observation in the [11-20] direction confirmed that the dislocation was an extended dislocation, with the Burgers vector experimentally found to be b = [1-210]a/3 + [0001]c which decomposes into two partial dislocations of bp1 = [0-110]a/3 + [0001]c/2 and bp2 = [1-100]a/3 + [0001]c/2. The dislocation vector u is [-12-10]a/3 + [0001]c. This technique is an effective method to analyze the dislocation characteristics of power electronics devices.

Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.

This paper describes material analysis and material design of high reliability solder resist (SR) with excellent performance for high density packaging. There is growing demand for higher speed and higher data bandwidth signal transmission for many applications, such as 5G communication, artificial intelligence (AI), and advanced driver-assistance systems (ADAS). Such applications require high density and high performance IC packaging with fine Cu wiring and high frequency signal transmission. Solder resist materials for such packaging need to satisfy many special properties, such as high resistance to Cu electrochemical migration, strong adhesion to low profile Cu layers, and accurate photo-lithography resolution. However, development of a solder resist material that has all the excellent properties above is highly challenging, because many of these properties are trade-off. Indeed, adhesion of conventional SR to low profile Cu layer dropped more than 80% after high temperature and moisture HAST condition. Additionally, photolithography resolution below 50 μm was highly challenging due to light scattering. To overcome the trade-offs, this research began with the detail material analysis of the organic and inorganic components in SR materials. First analysis in polymer structures showed that resin with less shrinkage and less hydrolysis increased the initial adhesion, as well as adhesion after high temperature and high moisture condition. Next study on filler type and surface treatment revealed that the organic and inorganic surface treatment were effective to improve adhesion stability and resolution. This can be explained by the higher electrical affinity and less light scattering. By integrating the fundamental analyses, a new SR with excellent adhesion stability (85% of initial adhesion), high photolithography resolution below 40 μm, and excellent Cu migration resistance below 8 μm L/S.

Rechargeable batteries constructed with high-energy-density metal anodes, such as zinc and lithium, often suffer from dendrite formation during high-rate charging, which can lead to short circuits and reduced battery life. Here we report a novel method of realizing high-rate charging of zinc anodes together with the suppression of zinc dendrite formation by remarkably accelerating the electrodeposition within the nanopores of a porous electrode. By tuning not only the affinity between the wall-surface of nanopores and water but also that between the zinc complex with polyvalent carboxylates and water, we can establish a condition under which a surface-induced phase transition (SIFT) occurs. With the occurrence of SIFT, the penetration of zinc complexes into the nanopores becomes quite fast toward the formation of a second phase within the nanopore where the concentration of zinc complexes is orders of magnitude higher than in the bulk solution. More specifically, we use a hydrophobic nanoporous electrode,...

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Sodium-ion battery is a potential alternative to replace lithium-ion battery, the present main actor in electrical energy storage technologies. A recently discovered cathode material Na2.5Fe1.75(SO4)3 (NFS) derives not only high energy density with very high voltage generation over 3.8 V, but also high-rate capability of reversible Na insertion as a result of large tunnels in the alluaudite structure. Here we applied high-temperature X-ray/neutron diffraction to unveil characteristic structural features related to major Na transport pathways. Thermal activation and nuclear density distribution of Na demonstrate one-dimensional Na diffusion channels parallel to [001] direction in full consistence with computational predictions. This feature would be common for the related (sulfo-)alluaudite system, forming emerging functional materials group for electrochemical applications.

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

This paper describes the demonstration of 10-μm diameter interlayer vias with 3.5-μm wide re-distribution layer copper wiring in a unique dry-film polymer dielectric, ZEONIF ZS100 (ZS100), suitable for panel-based high-density organic and glass interposers. The uniqueness of polymer dielectric includes low dielectric constant, low dielectric loss, low moisture uptake, and low surface roughness. The dry-film polymer dielectric was laminated on thin and low coefficient of thermal expansion organic or glass cores using double-side vacuum lamination processes. The ultrasmall microvias were drilled with 248-nm KrF excimer laser. Metallization by electroless and electrolytic copper plating successfully achieved formation of fully filled vias and copper traces simultaneously without any chemical-mechanical polishing. The processes demonstrated in this paper enable interposers with much finer bump pitch than current organic package technology. In addition, the processes can be scaled to large panels leading to lower cost than the previous work in fine pitch Si interposers fabricated through back-endof-line wafer processes.

To realize higher spatial resolution than conventional SEM-based nano-probing system, a novel Electron Beam Absorbed Current imaging system was newly developed using a Hitachi HD-2700 200 kV dedicated STEM. Its specimen holder accommodates a mechanical probe for current detection and TEM grid specimen. This holder also has a micrometer-based coarse positioning and piezoelectric-elements-based fine positioning mechanism respectively for X, Y and Z-axis probe control. The absorbed current from the probe and the specimen are displayed as an image by STEM software via EBAC amplifier. We successfully made a probing onto FIB-prepared lamella specimen of semiconductor device to get an electrical contact. EBAC and EBIC images were clearly visualized in higher spatial resolution.

This paper reports the demonstration of 2-5 µm embedded trench formation in dry film polymer dielectrics such as Ajinomoto build-up film (ABF) and Polyimide without using chemical mechanical polishing (CMP) process. The trenches in these dielectrics were formed by excimer laser ablation, followed by metallization of trenches by copper plating processes and overburden removal with surface planer tool. The materials and processes integrated in this work are scalable to large panel fabrication at much higher throughput, for interposers and high density fan-out packaging at lower cost and higher performance than silicon interposers.

This paper describes for the first time an innovative approach to improve re-distribution layer (RDL) yields in advanced semi-additive processes (SAP). An atmospheric pressure ozone based treatment is proposed as an alternative to oxygen plasma treatment. The ozone treatment process is scalable, being appropriate for process wafers up to large panels, and is suited for small feature sizes down to 1 micron that are required for interposers and future fan-out packages. The ozone process provides an environmentally friendly solution that can also replace wet cleaning processes, eliminating the need for hazardous chemicals that require abatement. The paper demonstrates the potential for two opportunities for integration of ozone treatment steps in the SAP flow for RDL fabrication. These particular steps are identified as 1) ozone treatment after dry film resist (DFR) patterning to improve the electrolytic copper plating yield and 2) removal of DFR residue prior to seed layer etch cleaning. Both these steps resulted in significantly improved RDL yields and demonstrate the feasibility of integrating ozone based cleans in high-yield, high volume cost effective manufacturing of RDL in Advanced Packaging. The paper also proposes ozone treatment as a higher throughput alternative to the plasma treatment process for electrolytic copper plating. Since the ozone gas is generated from oxygen, and reduced to oxygen upon process completion, no hazardous gas is required, or discharged into the atmosphere. To exhibit the scalability of the ozone treatment to both wafer-scale and panel-scale processing, two different types of copper seed layers, physical vapor deposition (PVD) Ti-Cu, and electroless plated copper, were evaluated. Samples were treated with either ozone or oxygen plasma, and the results were compared to a control sample with no treatment. After the photolithography step, in which 7 micron thick DFR laminated on the copper seed layers was resolved to 3 micron feature size, the substrates were subjected to ozone or plasma treatments. The subsequent water contact angle measurements show significant wettability improvement on the surfaces of substrates with copper seed layer, DFR, and DFR mesh patterned on a copper seed layer. Samples were then compared for the quality of the copper plating. Excellent copper metallization quality was achieved in the samples that had been treated with ozone and plasma due to the creation of a hydrophilic surface. An additional benefit emerged in that the ozone treatment was effective at 50 deg C, which minimized any impact on DFR stripping. The ozone treatment was also applied to clean the DFR residue after resist stripping and the results confirmed that the ozone process removed any remaining photoresist residue from the copper surface.

Interconnections between integrated circuits and print circuit boards are primarily achieved currently with organic packages at high I/O pitch. Organic packages, however, are limited by poor thermal and dimension stabilities for them to act as fine pitch interposers. To address these challenges, silicon interposers are being developed. Current silicon interposers, based on through-silicon via (TSV) techniques, suffer from high production cost, because of expensive CMOS-grade silicon, expensive TSV process and smaller wafer sizes. They also suffer from high electrical loss in spite of thin SiO 2 interfacial layers. This paper, for the first time, demonstrates a lower cost and higher performance silicon interposer. It is based on panel-based polycrystalline silicon with through-package vias (TPVs) and redistribution layers, and a simple and double-side process with thick polymer liner inside the TPV. Electrical modeling was carried out that shows the better electrical performance of polycrystalline silicon interposer compared with traditional single-crystalline silicon interposer. The polycrystalline silicon interposer test vehicles with up to four metal layers were demonstrated and characterized. The measurement results showed good electrical performance and matched well with the simulations.

This paper presents the design, analysis, and demonstration of an ultra-thin wireless local area network (WLAN) RF receiver module with chip-last embedded actives and embedded passives in a low-loss organic substrate using system-on-package approach. The overall thickness of the module, including the embedded dies, is 160 μm- more than 3× thickness reduction compared to current wire-bond and flip-chip packages. The receiver module consists of gallium arsenide low-noise amplifier (LNA) dies, chip-last embedded in an ultrathin, low-loss organic substrate, and connected to a substrate-embedded three-metal-layer band-pass filter (BPF) in close proximity. Full-wave electromagnetic simulation was performed on a 3-D model of the designed receiver module to obtain its two-port scattering parameters (S-parameters) and to study noise coupling between the power-supply network and the signal path. The receiver module was then fabricated, tested for yield of the BPF, assembled and characterized, and the measured results were correlated with simulation. The BPF dimensions in the package were 1.5 mm × 2.9 mm × 0.15 mm, and its measured pass-band insertion loss was 2.3 dB with more than 15 dB return loss. The receiver module (LNA + BPF) dimensions were 5.5 mm ×2 mm ×0.16 mm, and it had a measured peak gain of 11 dB with more than 30 dB attenuation in the adjacent-band, indicating excellent performance in a miniaturized form-factor.

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15–40 $\mu{\rm m}$ in diameter) in 30- $\mu{\rm m}$ thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 $\mu{\rm m}$ ) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 $\mu{\rm m}$ at 27- $\mu{\rm m}$ pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss ${ at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

The conventional KOH etching method at elevated temperatures is an easy way to study SiC dislocations, but presents problems due to an increased etch rate. Here, we examine the application of low temperature KOH treatment for the analysis of dislocation cores and etch pits in SiC. A low energy scanning electron microscope (SEM) is effective to classify dislocation kinds. The scanning transmission electron microscope (STEM) observation of thick samples prepared by the in situ micro-sampling technique enables evaluation of detailed dislocation properties.

InGaAs surface nitridation effect on La2O3/InGaAs interface has been investigated. It was found that by controlling nitridation conditions such as temperature interface quality can be improved. Also a new covalent structure based on nitridated Si and La2O3 is proposed to reduce dielectric and substrate intermixing, thus improving the high-k/InGaAs interface. High electron mobility of III-V material, in particular InGaAs, has made them a promising candidate to replace channel in Si-based metal-oxide-semiconductor field effect transistors (MOSFETs) [1]. In order to realize high performance III-V devices, the interface at high-k gate oxide and substrate surface must be improved [2]. Various interface control methods such as sulfur treatment and nitridation have been proposed in order to improve interface quality [3]. The most promising results have been reported on Al2O3-based capacitors which is a dielectric with covalent nature. However the low dielectric constant value of Al2O3 (k~9) makes it unsuitable for device scaling. In this study we have investigated the formation of a covalent interface by means of insertion and nitridation of a thin Si layer at La2O3/InGaAs interface. La2O3 (k~30) is recognized as a next-generation high-k material. A Si-doped n-In0.53Ga0.47As epiaxially grown on InP substrate was used. After oxide removal by HF, nitridation was performed by radical gun prior to La2O3 deposition for 5min. Amount of nitrogen dose was estimated at ~1.5x10 atoms/cm by SIMS. La2O3 layer was deposited by e-beam evaporation and W gate electrode was in situ deposited by RF magnetron sputtering. Post-metallization anneals (PMA) were carried out in forming gas (N2:H2= 97:3%) ambient. Fig. 1 shows capacitance-voltage (C-V) characteristic of W/La2O3/In0.53Ga0.47As annealed in F.G at 370 C with (a) and without (b) surface nitridation at 200 C. Low frequency capacitance response in negative gate bias is suppressed for nitridated sample which is an indicator of improved interface. Optimum surface passivation was obtained for nitridation at a substrate temperature of 200 C (fig. 2). Performing Nitridation after a thin Si layer insertion (fig. 3 (a)) further improved the C-V characteristics of the device, evident from smaller frequency dispersion in accumulation condition (fig. 3 (b)). In conclusion, nitridation was shown to be an effective interface passivation method. Forming a LaO-Si-N structure with covalent nature further improved C-V characteristics of the capacitors.

The metal/InGaAs Schottky devices with Ni, TiN and stacked Ni/Si were fabricated. J-V and C-V characteristics were measured and Schottky barrier height was calculated.

Impacts of structural transformations of top and bottom interface of metal/GeO2/Ge structure on electrical properties were investigated. The GeO2/Ge interface that was formed by low temperature oxidation achieved negligible hysteresis because of suppressing GeO volatilization. On the other hand, the metal/GeO2 interface with post metal deposition annealing attained disappearance of VFB shift. XPS and TDS measurements show that GeOx at the interface of the as-deposited metal/GeO2 vanished after annealing. It suggests that the improvement of the VFB shift was achieved by volatilization of GeOx including defects at the metal/GeO2 interface.

The fabrication procedure for silicon carbide power metal oxide semiconductor field-effect transistors can be improved through simultaneous formation (i.e., using the same contact materials and a one-step annealing process) of ohmic contacts on both the n-source and p-well regions. We have succeeded in the simultaneous formation of Ni/Al ohmic contacts to n- and p-type SiC after annealing at 1000°C for 5 min in an ultrahigh vacuum. Ohmic contacts to n-type SiC were found when the Al-layer thickness was less than about 6 nm, while ohmic contacts to p-type SiC were observed for an Al-layer thickness greater than about 5 nm. Only the contacts with an Al-layer thickness in the range of 5 nm to 6 nm exhibited ohmic behavior to both n- and p-type SiC, with a specific contact resistance of 1.8 × 10−4 Ω cm2 and 1.2 × 10−2 Ω cm2 for n- and p-type SiC, respectively. An about 100-nm-thick contact layer was uniformly formed on the SiC substrate, and polycrystalline δ-Ni2Si(Al) grains were formed at the contact/SiC interface. In the samples that exhibited ohmic behavior to both n- and p-type SiC, the distribution of the Al/Ni ratios in the δ-Ni2Si(Al) grains was larger than that observed for any of the samples that showed ohmic behavior to either n- or p-type SiC. Furthermore, the grain size of the δ-Ni2Si(Al) grains in the samples showing ohmic behavior to both n- and p-type SiC was smaller than the grains in any of the samples that showed ohmic behavior to either n- or p-type SiC. Thus, the large distribution in the Al/Ni ratios and a fine microstructure were found to be characteristic of the ohmic contacts to both n- and p-type SiC. Grains with a low Al concentration correspond to ohmic contacts to n-type SiC, while grains with a high Al concentration correspond to ohmic contacts to p-type SiC.

Fully regioregular poly[(2-methoxy-5-(3′,7′-dimethyloctyloxy))-1,4-phenylenevinylene]s (MDMO-PPVs) synthesized by the Horner route were utilized for polymer photovoltaic devices, and their performance was compared with that of regiorandom MDMO-PPVs. The mixture films of the regioregular MDMO-PPVs and 1-[3-(methoxycarbonyl)propyl]-1-phenyl-(6,6)-C61 (PCBM) were successfully fabricated by spin coating using a hot chlorobenzene solution. Significant improvements in fill factor (FF) and short circuit current (ISC) were observed for the devices with regioregular MDMO-PPV compared with those for devices with regiorandom MDMO-PPV. A power conversion efficiency of 3.1% was achieved with regioregular MDMO-PPV under AM1.5 illumination, which is the highest efficiency reported for the PPV:PCBM system so far, whereas a power conversion efficiency of only 1.7% was achieved with regiorandom MDMO-PPV. It is concluded that both higher hole mobility resulting from the higher crystallinity of the polymer and better mixing ...

Phase transitions in Bi4-xSmxTi3O12 single crystals in the Sm concentration range of x≤0.61 were studied. The phase transition near 670 °C was found to remain almost unchanged in the concentration range of 0≤x≤0.61. Below the transition temperature of 670 °C, dielectric anomaly showing phase transitions was found in BSmT-x, depending on the concentration x. It was confirmed that the triggered transition from the tetragonal phase to the monoclinic phase, observed in Bi4Ti3O12, splits into two phase transitions by adding Sm cations, i.e., from the tetragonal phase to the orthorhombic phase and further to the monoclinic phase. The temperature-concentration phase diagram of the BSmT-x system was clarified.

This paper describes the first demonstration of 8–10µm diameter micro-vias at 20µm pitch in ultra-thin dry-film polymer dielectrics to achieve high-density and low-cost redistribution layers (RDL) on panel-based glass and organic interposers. A polymer dielectric dry-film, ZEONIF ZS100, at 10µm thickness was double side laminated on thin and low CTE glass and organic substrates. Micro-via arrays at 20µm pitch were formed by 248nm KrF excimer laser ablation using mask projection scanning, and metallized by a semi-additive process (SAP) using electroless and electrolytic copper plating, with no chemical-mechanical polishing to form fully filled via structures. Fully-filled micro-vias at 20um were achieved using processes scalable to large panels for low-cost and high-density 2.5D and 3D interposers.

This paper presents a comprehensive study on the fundamental factors that impact the scalability of organic interposers to 40µm area array bump pitch, leading to the design and fabrication of ultra-thin and low CTE organic interposers at 40µm pitch. Silicon interposers were the first substrates used for 2.5D integration of logic and memory ICs at close proximity. However, the high cost and electrical loss of wafer back end of line (BEOL) silicon interposers has fueled the need for fine-pitch organic interposers. Organic substrates face two primary challenges in achieving finer I/O pitch: layer-to-layer mis-registration during copper-polymer re-distribution layer (RDL) fabrication due to the thermo-mechanical stability issue of organic laminate cores, and warpage during chip assembly on thin core substrates. This paper studies these two fundamental factors by finite element modeling (FEM) and experimental characterization, resulting in RDL design guidelines for low mis-registration and warpage. Reducing the copper thickness in each layer as well as the thickness of the polymer dielectric to below 10µm, resulted in significant reduction in CTE mismatch-induced stresses at different interfaces. The modeling-based design was verified by fabrication of a multi-layer RDL stack on 100µm thin low coefficient of thermal expansion (CTE) organic cores with ultra-thin build-up layers to achieve a bump pitch of 40µm. The assembly of chips on the thin organic interposer was optimized to minimize the warpage, leading to the demonstration of two-chip 2.5D organic interposers.

There are many differences of bond regulations between the AIJ code and the ACI code. In the AIJ code, bond stresses within a distance d from the end of a beam are assumed to be zero because of tension shift, where d is effective depth. By contrast, the ACI code does not. Another difference is checking for continuous bars. The AIJ code considers bond failure of continuous bars although the ACI code does not. The objective of this study is to verify these bond regulations.Four RC beam specimens with single layered bars were tested. Test variables were length and the number of cut-off bars. Bond failure was observed before flexural yielding in all the specimens, and tension shift was not observed. The postulate in the ACI code is appropriate in such cases. Bond failure occurred along not only cut-off bars but continuous bars. The observed bond strengths of the continuous bars almost agreed with those calculated from the AIJ code.

The authors investigated real-time monitoring of charge accumulation during pulse-time-modulated plasma processes by using their developed on-wafer monitoring chip. The charge accumulation potential between the top surface and the bottom in a SiO2 contact structure was measured during pulse-time-modulated plasma exposure with an on-wafer monitoring device. In conventional plasma with rf bias, the electron shading effect could be clearly observed as the potential difference between the wafer surface and the contact-hole bottom. Conversely, the accumulated charge in the pulse-time-modulated operation was drastically decreased. Time-resolved electron and ion flows to the SiO2 contact hole were clarified by the on-wafer monitoring. Accordingly, it was confirmed that the on-wafer monitoring is a very effective tool for investigating the local charge accumulation in actual device structures.

SiO2 contact-hole etching with a high-aspect ratio is a key process in fabricating ultra-large scale integrated devices. However, charge accumulation in contact holes during plasma etching causes serious problems, such as charge-build-up damage, etching-stop, and microloading effects. Therefore, understanding the mechanism behind this electric charge accumulation and controlling the plasma etching processes would be very important to achieve the next-generation semiconductor devices. We found, through our previous research, that deposited fluorocarbon film in contact holes had high electric conductivity because of ion bombardment. In this experiment, we investigated the build up of charging potential during plasma processes by in situ on-wafer monitoring to control charge accumulation in the contact holes. We developed an on-wafer monitoring device to measure the charging potential in SiO2 contact holes (aspect ratio=5.7). The dc potential of the SiO2 contact hole top and bottom surfaces were measured dur...

The use of electrical discharge pulses is a new method to prepare thin films. The conventional phosphor thin film preparation technology uses rf sputtering or vacuum vapor deposition. However, thin films prepared by conventional methods are formed in amorphousness on the substrates. In contrast, this new method uses the electrical discharge energy between an electrode and a conductive substrate. When an electrical pulse is discharged between the electrode and the substrate, the electrode material, which is zinc and phosphor, moves to the substrate. Consequently, this new method can be used to produce light-emitting devices. In this study, we used the phosphor Zn2SiO4:Mn2+. We were able to prepare luminescent Zn2SiO4:Mn2+ films using a discharge currant of 10 A, at a voltage of 80 V and weight ratio of zinc to Zn2SiO4:Mn2+ of 6:4. We evaluated the resultant films with scanning electron microscopy (SEM) and X-ray diffraction (XRD).

Super elastic alloy (SEA) has the characteristic of two-way deformation by heating and cooling under prestressed condition. The characteristic makes it possible to realize an actuator of flexible, compact, and quiet. Therefore, SEA can be applied to such robots for medical, assist, welfare, automatic door, and so on. However, there are many difficulties in its control as actuator because SEA shows strong non-linear behavior on its deformation process. In this study, the measurement system of state quantities on the non-linear characteristics of SEA is constructed to control the deformation of it as practical actuator. Here, the actuator made by SEA is heated by electric current. And then, electrical systems are also developed to measure the state quantities of temperature, strain and electric resistivity of SEA during the Joule heating for its mechatronical control. In addition, the measurement of the electric resistivity on the process of heating and cooling is performed by applying pulse voltage for perform stable and accurate measurement even at a low voltage is applied.

In this paper, a large 2.5D glass interposer is demonstrated with 50 um chip-level interconnect (FLI), 3/3 um line and space (L/S) escape routing, and six metal layers, which are targeted for JEDEC high bandwidth memory (HBM). Our routing design suggests that double sided panel processing with 3/3 um L/S can accommodate required signal lines for HBM. Then, 3/3 um L/S transmission lines on 25mm × 30mm glass interposers with 300 um core thickness can be realized by utilizing semi additive process. Finally, 10mm × 10m dies with daisy chains can be successfully bonded to 25mm × 30mm glass interposer with 6 metal lines using copper microbumps with SnAg solder caps.